From patchwork Sun Dec 8 12:22:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1205631 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47W5H31Zfmz9sP3 for ; Sun, 8 Dec 2019 23:29:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Il9fbsUO"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47W5H26wnkzDqPf for ; Sun, 8 Dec 2019 23:29:18 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::1030; helo=mail-pj1-x1030.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Il9fbsUO"; dkim-atps=neutral Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47W58j51fWzDqFL for ; Sun, 8 Dec 2019 23:23:49 +1100 (AEDT) Received: by mail-pj1-x1030.google.com with SMTP id g4so4643087pjs.10 for ; Sun, 08 Dec 2019 04:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5LLfbAweH8IeROJ/vHuL11tEKhpy3FiIGdKn/fTeIz8=; b=Il9fbsUO7L/nv78G7xzbbWUAmuMd0IeGqfMtMnC7ewkRyO+hZ44dPXllAJsZ0MwuKt S8Pv3rzW4jVnejn5ZAC/3buNIWZwXgwNbTnvVttNC5e6QW6zOFVmuHuMZK8PBadF0ORY JghEjV83+j/67JAA3vMfuYn3at0sKNffo2ET/eNvhqDhY9tkT4347gV0d4p/pFNkuJMY 06sZbqhnOghhiWoy/S7+jWGOEw4F+eXExY+aRockRMt2UToSTyRwASafolO3g9QdJrXo rbXGPUG8VZ69S+s9dELU+hs6vNX0tOV3c1dJoZZoPevAQta7HsuEbgogUJthcsjCLqh2 Q9Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5LLfbAweH8IeROJ/vHuL11tEKhpy3FiIGdKn/fTeIz8=; b=qXyd2pYpLkXXPZIIDUZ4sBq4+4HfHRAtUC4dbPrsuJ8SXAZ1QbwL0mzoa1sTqpJqOZ j0xO0GORoPocfuhj7mA8mO82Bsc8jR+OG9YTb0vOz/ApqvWeyTDxsbm9JIcV0s+jTEwk ILXHqDjelkbI1Crj8KD1N29cD3vA1jhee6jdO2yJLZ3YTxAwZBRQlcHwRi0VJ1KIyMXj folrUnsHure0w0XQivdh1/x1O4/QF89ahtFVkJKZPXw5wyqweNd/E8CUOOpnNTi0in4m ts6VKwcmcVv6TrjjXM2tYiqGxWbMhrlnWqUbuo7Oc9sxYdY1mIUXQl2P5SCKAr0+BOIR l0wQ== X-Gm-Message-State: APjAAAWMD6OeZybtA/ADZ+sJ28BLlI3DVb7pJTcuNMsCRRyUl+/y6kcX 72q3CuI7ht5UKu8j/VqYzduESJTx X-Google-Smtp-Source: APXvYqynQ3sk3qfcTlWoFCvUM8VJcxYzftlBelkgBTHfWLubENCXG1pUFpktfVto5YMGXge/Dkdz6w== X-Received: by 2002:a17:902:5999:: with SMTP id p25mr25261165pli.261.1575807825333; Sun, 08 Dec 2019 04:23:45 -0800 (PST) Received: from bobo.local0.net ([202.21.15.182]) by smtp.gmail.com with ESMTPSA id i9sm23741866pfk.24.2019.12.08.04.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Dec 2019 04:23:44 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 8 Dec 2019 22:22:51 +1000 Message-Id: <20191208122312.12837-11-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191208122312.12837-1-npiggin@gmail.com> References: <20191208122312.12837-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v10 10/31] io: endian conversions for io accessors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This requires a small change to flash drivers which assumed 4-byte LPC reads would not change endian. _raw accessors could be added if this becomes a signifcant pattern, but for now this hack works. Signed-off-by: Nicholas Piggin --- include/io.h | 79 ++++++++++++++++++++++++++++++------- libflash/ipmi-hiomap.c | 20 +++++++--- libflash/mbox-flash.c | 20 +++++++--- libflash/test/mbox-server.c | 31 ++++++++++++++- 4 files changed, 121 insertions(+), 29 deletions(-) diff --git a/include/io.h b/include/io.h index c6203a274..57dddd49f 100644 --- a/include/io.h +++ b/include/io.h @@ -9,6 +9,7 @@ #include #include #include +#include #include /* @@ -35,10 +36,10 @@ static inline uint8_t in_8(const volatile uint8_t *addr) static inline uint16_t __in_be16(const volatile uint16_t *addr) { - uint16_t val; + __be16 val; asm volatile("lhzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be16_to_cpu(val); } static inline uint16_t in_be16(const volatile uint16_t *addr) @@ -47,17 +48,26 @@ static inline uint16_t in_be16(const volatile uint16_t *addr) return __in_be16(addr); } +static inline uint16_t __in_le16(const volatile uint16_t *addr) +{ + __le16 val; + asm volatile("lhzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le16_to_cpu(val); +} + static inline uint16_t in_le16(const volatile uint16_t *addr) { - return bswap_16(in_be16(addr)); + sync(); + return __in_le16(addr); } static inline uint32_t __in_be32(const volatile uint32_t *addr) { - uint32_t val; + __be32 val; asm volatile("lwzcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be32_to_cpu(val); } static inline uint32_t in_be32(const volatile uint32_t *addr) @@ -66,17 +76,26 @@ static inline uint32_t in_be32(const volatile uint32_t *addr) return __in_be32(addr); } +static inline uint32_t __in_le32(const volatile uint32_t *addr) +{ + __le32 val; + asm volatile("lwzcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le32_to_cpu(val); +} + static inline uint32_t in_le32(const volatile uint32_t *addr) { - return bswap_32(in_be32(addr)); + sync(); + return __in_le32(addr); } static inline uint64_t __in_be64(const volatile uint64_t *addr) { - uint64_t val; + __be64 val; asm volatile("ldcix %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr) : "memory"); - return val; + return be64_to_cpu(val); } static inline uint64_t in_be64(const volatile uint64_t *addr) @@ -85,9 +104,18 @@ static inline uint64_t in_be64(const volatile uint64_t *addr) return __in_be64(addr); } +static inline uint64_t __in_le64(const volatile uint64_t *addr) +{ + __le64 val; + asm volatile("ldcix %0,0,%1" : + "=r"(val) : "r"(addr), "m"(*addr) : "memory"); + return le64_to_cpu(val); +} + static inline uint64_t in_le64(const volatile uint64_t *addr) { - return bswap_64(in_be64(addr)); + sync(); + return __in_le64(addr); } static inline void __out_8(volatile uint8_t *addr, uint8_t val) @@ -105,7 +133,7 @@ static inline void out_8(volatile uint8_t *addr, uint8_t val) static inline void __out_be16(volatile uint16_t *addr, uint16_t val) { asm volatile("sthcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be16(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be16(volatile uint16_t *addr, uint16_t val) @@ -114,15 +142,22 @@ static inline void out_be16(volatile uint16_t *addr, uint16_t val) return __out_be16(addr, val); } +static inline void __out_le16(volatile uint16_t *addr, uint16_t val) +{ + asm volatile("sthcix %0,0,%1" + : : "r"(cpu_to_le16(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le16(volatile uint16_t *addr, uint16_t val) { - out_be16(addr, bswap_16(val)); + sync(); + return __out_le16(addr, val); } static inline void __out_be32(volatile uint32_t *addr, uint32_t val) { asm volatile("stwcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be32(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be32(volatile uint32_t *addr, uint32_t val) @@ -131,15 +166,22 @@ static inline void out_be32(volatile uint32_t *addr, uint32_t val) return __out_be32(addr, val); } +static inline void __out_le32(volatile uint32_t *addr, uint32_t val) +{ + asm volatile("stwcix %0,0,%1" + : : "r"(cpu_to_le32(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le32(volatile uint32_t *addr, uint32_t val) { - out_be32(addr, bswap_32(val)); + sync(); + return __out_le32(addr, val); } static inline void __out_be64(volatile uint64_t *addr, uint64_t val) { asm volatile("stdcix %0,0,%1" - : : "r"(val), "r"(addr), "m"(*addr) : "memory"); + : : "r"(cpu_to_be64(val)), "r"(addr), "m"(*addr) : "memory"); } static inline void out_be64(volatile uint64_t *addr, uint64_t val) @@ -148,9 +190,16 @@ static inline void out_be64(volatile uint64_t *addr, uint64_t val) return __out_be64(addr, val); } +static inline void __out_le64(volatile uint64_t *addr, uint64_t val) +{ + asm volatile("stdcix %0,0,%1" + : : "r"(cpu_to_le64(val)), "r"(addr), "m"(*addr) : "memory"); +} + static inline void out_le64(volatile uint64_t *addr, uint64_t val) { - out_be64(addr, bswap_64(val)); + sync(); + return __out_le64(addr, val); } /* Assistant to macros used to access PCI config space */ diff --git a/libflash/ipmi-hiomap.c b/libflash/ipmi-hiomap.c index 0328101c6..821d28dd9 100644 --- a/libflash/ipmi-hiomap.c +++ b/libflash/ipmi-hiomap.c @@ -570,8 +570,13 @@ static int lpc_window_read(struct ipmi_hiomap *ctx, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(__be32 *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -615,12 +620,15 @@ static int lpc_window_write(struct ipmi_hiomap *ctx, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(__be32 *)buf); + + rc = lpc_write(OPAL_LPC_FW, off, dat, 4); chunk = 4; } else { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + uint8_t dat = *(uint8_t *)buf; + + rc = lpc_write(OPAL_LPC_FW, off, dat, 1); chunk = 1; } if (rc) { diff --git a/libflash/mbox-flash.c b/libflash/mbox-flash.c index 9d47fe7ea..5df020f55 100644 --- a/libflash/mbox-flash.c +++ b/libflash/mbox-flash.c @@ -159,8 +159,13 @@ static int lpc_window_read(struct mbox_flash_data *mbox_flash, uint32_t pos, /* XXX: make this read until it's aligned */ if (len > 3 && !(off & 3)) { rc = lpc_read(OPAL_LPC_FW, off, &dat, 4); - if (!rc) - *(uint32_t *)buf = dat; + if (!rc) { + /* + * lpc_read swaps to CPU endian but it's not + * really a 32-bit value, so convert back. + */ + *(__be32 *)buf = cpu_to_be32(dat); + } chunk = 4; } else { rc = lpc_read(OPAL_LPC_FW, off, &dat, 1); @@ -194,12 +199,15 @@ static int lpc_window_write(struct mbox_flash_data *mbox_flash, uint32_t pos, uint32_t chunk; if (len > 3 && !(off & 3)) { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint32_t *)buf, 4); + /* endian swap: see lpc_window_write */ + uint32_t dat = be32_to_cpu(*(__be32 *)buf); + + rc = lpc_write(OPAL_LPC_FW, off, dat, 4); chunk = 4; } else { - rc = lpc_write(OPAL_LPC_FW, off, - *(uint8_t *)buf, 1); + uint8_t dat = *(uint8_t *)buf; + + rc = lpc_write(OPAL_LPC_FW, off, dat, 1); chunk = 1; } if (rc) { diff --git a/libflash/test/mbox-server.c b/libflash/test/mbox-server.c index 3f879dfa4..59786ca14 100644 --- a/libflash/test/mbox-server.c +++ b/libflash/test/mbox-server.c @@ -100,7 +100,21 @@ int64_t lpc_read(enum OpalLPCAddressType __unused addr_type, uint32_t addr, /* Let it read from a write window... Spec says it ok! */ if (!check_window(addr, sz) || server_state.win_type == WIN_CLOSED) return 1; - memcpy(data, server_state.lpc_base + addr, sz); + + switch (sz) { + case 1: + *(uint8_t *)data = *(uint8_t *)(server_state.lpc_base + addr); + break; + case 2: + *(uint16_t *)data = be16_to_cpu(*(uint16_t *)(server_state.lpc_base + addr)); + break; + case 4: + *(uint32_t *)data = be32_to_cpu(*(uint32_t *)(server_state.lpc_base + addr)); + break; + default: + prerror("Invalid data size %d\n", sz); + return 1; + } return 0; } @@ -111,7 +125,20 @@ int64_t lpc_write(enum OpalLPCAddressType __unused addr_type, uint32_t addr, { if (!check_window(addr, sz) || server_state.win_type != WIN_WRITE) return 1; - memcpy(server_state.lpc_base + addr, &data, sz); + switch (sz) { + case 1: + *(uint8_t *)(server_state.lpc_base + addr) = data; + break; + case 2: + *(uint16_t *)(server_state.lpc_base + addr) = cpu_to_be16(data); + break; + case 4: + *(uint32_t *)(server_state.lpc_base + addr) = cpu_to_be32(data); + break; + default: + prerror("Invalid data size %d\n", sz); + return 1; + } return 0; }