@@ -255,7 +255,7 @@ static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *paren
pd->is_bridge = (htype & 0x7f) != 0;
pd->is_vf = false;
pd->scan_map = 0xffffffff; /* Default */
- pd->primary_bus = (bdfn >> 8);
+ pd->primary_bus = PCI_BUS_NUM(bdfn);
pci_init_capabilities(phb, pd);
@@ -784,7 +784,7 @@ static int64_t npu_set_pe(struct phb *phb,
* bus number is zero.
*/
dev = bdfn_to_npu_dev(p, bdfn);
- if ((bdfn >> 8) || !dev)
+ if (PCI_BUS_NUM(bdfn) || !dev)
return OPAL_PARAMETER;
link_idx = dev->index;
@@ -28,8 +28,8 @@
#define NPU3DEVLOG(l, dev, fmt, a...) \
prlog(l, "NPU#%04x:%02x:%02x.%x " fmt, \
(dev)->npu->nvlink.phb.opal_id, \
- (dev)->nvlink.pvd->bdfn >> 8 & 0xff, \
- (dev)->nvlink.pvd->bdfn >> 3 & 0x1f, \
+ PCI_BUS_NUM((dev)->nvlink.pvd->bdfn), \
+ (dev)->nvlink.pvd->bdfn >> 3 & 0x1f, \
(dev)->nvlink.pvd->bdfn & 0x7, ##a)
#define NPU3DEVDBG(dev, fmt, a...) NPU3DEVLOG(PR_DEBUG, dev, fmt, ##a)
#define NPU3DEVINF(dev, fmt, a...) NPU3DEVLOG(PR_INFO, dev, fmt, ##a)
@@ -1594,7 +1594,7 @@ int64_t npu3_init_context(struct phb *phb, uint64_t msr, uint64_t bdf)
lparshort = GETFIELD(NPU3_XTS_BDF_MAP_LPARSHORT, map);
NPU3DBG(npu, "Found LPARSHORT 0x%x for bdf %02llx:%02llx.%llx\n",
- lparshort, bdf >> 8 & 0xff, bdf >> 3 & 0x1f, bdf & 0x7);
+ lparshort, PCI_BUS_NUM(bdf), bdf >> 3 & 0x1f, bdf & 0x7);
rc = npu3_init_context_pid(npu, lparshort, msr);
if (rc)
@@ -1711,7 +1711,7 @@ int64_t npu3_map_lpar(struct phb *phb, uint64_t bdf, uint64_t lparid,
if (!dev || dev->nvlink.gpu->bdfn != bdf) {
NPU3ERR(npu, "Can't find a link for bdf %02llx:%02llx.%llx\n",
- bdf >> 8 & 0xff, bdf >> 3 & 0x1f, bdf & 0x7);
+ PCI_BUS_NUM(bdf), bdf >> 3 & 0x1f, bdf & 0x7);
rc = OPAL_PARAMETER;
goto out;
}
@@ -126,7 +126,7 @@ static int64_t phb3_pcicfg_check(struct phb3 *p, uint32_t bdfn,
* error state if we try to probe beyond that, so let's
* avoid that and just return an error to Linux
*/
- if ((bdfn >> 8) == 0 && (bdfn & 0xff))
+ if (PCI_BUS_NUM(bdfn) == 0 && (bdfn & 0xff))
return OPAL_HARDWARE;
/* Check PHB state */
@@ -3278,7 +3278,7 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint64_t pe_number,
if (prefer == 0xffffull) {
if (is_bus_pe) {
m = PHB_PAPR_ERR_INJ_MASK_CFG;
- prefer = SETFIELD(m, 0x0ull, (bdfn >> 8));
+ prefer = SETFIELD(m, 0x0ull, PCI_BUS_NUM(bdfn));
} else {
m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL;
prefer = SETFIELD(m, 0x0ull, bdfn);
@@ -3293,7 +3293,7 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint64_t pe_number,
}
if (is_bus_pe &&
- GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == (bdfn >> 8)) {
+ GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == PCI_BUS_NUM(bdfn)) {
a = addr;
break;
}
@@ -258,7 +258,7 @@ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn,
* error state if we try to probe beyond that, so let's
* avoid that and just return an error to Linux
*/
- if ((bdfn >> 8) == 0 && (bdfn & 0xff))
+ if (PCI_BUS_NUM(bdfn) == 0 && (bdfn & 0xff))
return OPAL_HARDWARE;
/* Check PHB state */
@@ -3812,7 +3812,7 @@ static int64_t phb4_err_inject_cfg(struct phb4 *phb, uint64_t pe_number,
if (prefer == 0xffffull) {
if (is_bus_pe) {
m = PHB_PAPR_ERR_INJ_MASK_CFG;
- prefer = SETFIELD(m, 0x0ull, (bdfn >> 8));
+ prefer = SETFIELD(m, 0x0ull, PCI_BUS_NUM(bdfn));
} else {
m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL;
prefer = SETFIELD(m, 0x0ull, bdfn);
@@ -3827,7 +3827,7 @@ static int64_t phb4_err_inject_cfg(struct phb4 *phb, uint64_t pe_number,
}
if (is_bus_pe &&
- GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == (bdfn >> 8)) {
+ GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == PCI_BUS_NUM(bdfn)) {
a = addr;
break;
}
@@ -18,7 +18,7 @@
#define NPU2DEVLOG(l, p, fmt, a...) prlog(l, "NPU%d:%d:%d.%d " fmt, \
(p)->npu->phb_nvlink.opal_id, \
- ((p)->bdfn >> 8) & 0xff, \
+ PCI_BUS_NUM((p)->bdfn), \
((p)->bdfn >> 3) & 0x1f, \
(p)->bdfn & 0x7, ##a)
#define NPU2DEVDBG(p, fmt, a...) NPU2DEVLOG(PR_DEBUG, p, fmt, ##a)
@@ -13,22 +13,22 @@
#define PCITRACE(_p, _bdfn, fmt, a...) \
prlog(PR_TRACE, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
- ((_bdfn) >> 8) & 0xff, \
+ PCI_BUS_NUM(_bdfn), \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCIDBG(_p, _bdfn, fmt, a...) \
prlog(PR_DEBUG, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
- ((_bdfn) >> 8) & 0xff, \
+ PCI_BUS_NUM(_bdfn), \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCINOTICE(_p, _bdfn, fmt, a...) \
prlog(PR_NOTICE, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
- ((_bdfn) >> 8) & 0xff, \
+ PCI_BUS_NUM(_bdfn), \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
#define PCIERR(_p, _bdfn, fmt, a...) \
prlog(PR_ERR, "PHB#%04x:%02x:%02x.%x " fmt, \
(_p)->opal_id, \
- ((_bdfn) >> 8) & 0xff, \
+ PCI_BUS_NUM(_bdfn), \
((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
struct pci_device;
@@ -137,6 +137,9 @@ static inline bool is_pow2(unsigned long val)
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
+/* PCI Geographical Addressing */
+#define PCI_BUS_NUM(bdfn) (((bdfn) >> 8) & 0xff)
+
/* Clean the stray high bit which the FSP inserts: we only have 52 bits real */
static inline u64 cleanup_addr(u64 addr)
{
@@ -267,7 +267,7 @@ static int pciinv_walk(struct phb *phb, struct pci_device *pd, void *data)
/* Fill the PCI device inventory description */
pack->device.domain_num = cpu_to_be16(phb->opal_id & 0xffff);
- pack->device.bus_num = (pd->bdfn >> 8) & 0xff;
+ pack->device.bus_num = PCI_BUS_NUM(pd->bdfn);
pack->device.device_num = (pd->bdfn >> 3) & 0x1f;
pack->device.func_num = pd->bdfn & 0x7;
pack->device.vendor_id = cpu_to_be16(PCI_VENDOR_ID(pd->vdid));
Currently when the Bus Number bits of a BDF are needed the bit operations to get it are free coded. There are many places where the Bus Number is used, so make a macro to use instead of free coding it everytime. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> --- core/pci.c | 2 +- hw/npu.c | 2 +- hw/npu3-nvlink.c | 8 ++++---- hw/phb3.c | 6 +++--- hw/phb4.c | 6 +++--- include/npu2.h | 2 +- include/pci.h | 8 ++++---- include/skiboot.h | 3 +++ platforms/astbmc/vesnin.c | 2 +- 9 files changed, 21 insertions(+), 18 deletions(-)