From patchwork Wed Aug 7 06:24:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1143284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 463M200ccSz9sBF for ; Wed, 7 Aug 2019 16:25:28 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OciSUs7/"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 463M1z6GWnzDr6T for ; Wed, 7 Aug 2019 16:25:27 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::643; helo=mail-pl1-x643.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OciSUs7/"; dkim-atps=neutral Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 463M1L4MyWzDqwp for ; Wed, 7 Aug 2019 16:24:54 +1000 (AEST) Received: by mail-pl1-x643.google.com with SMTP id k8so39134253plt.3 for ; Tue, 06 Aug 2019 23:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GjPRt1eZp28kdmyd8FeTSrMCYl8fXk+XGOFtD7VSFj8=; b=OciSUs7/ox7W5MJ/XcwFhZzOVTan+MeTmZ1X4phVYvuyOxSCbD/mX54qhyfInltb/U +PBCYy5UyFQ9CcTiECxbHKZGmmFZJk/X1Sn4vgVXYb4AcI42+IxpiDIoBqIQthsPnSnJ 9PIZ9zEmRSH24LbOrigVave5sKOak0vFHyIfcAAjRm/Lx1Sk3xCL6Ml69yaJKq7n17hN E6L7vfYP5333VGEZrziw7vpduDI3fVCrMj3Aw9av0Vdsax77tJjjCAbTvt/bvgSEsja9 iqR7X7hSVr3yigSh/7t2uQ+MPnjHBoC/CbZhEEVB/Xsp3QX0OB7K5IJkeqx2mf3ltpxA z0cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GjPRt1eZp28kdmyd8FeTSrMCYl8fXk+XGOFtD7VSFj8=; b=Sqoe1Tt1uBgpJhfNzLAx1KsK+SBl3XvDWdp1B23qnTOKrMG42J+/2qX3XtZsO5RHiZ zA9r7eMgrxlN74H3EfcgAmvR9MIdUt6CXDpQRYH1U+SOOs6Z9NAznyI/oj10fJZjHIDn bORWTXTnrzM2b2q7k8mdvs1aXFmOFVwRNHMgJfO0r761jeBs/khpuN8HaqJpoA+bvf6d +H/U1qednZ9x8wKOJ3oeSQR6sPAqY2Luo6bIuCiVPQeWf//7IPH0DXUzApQ4IgHAmD37 lxcEbhom5kN/rdat44/L24nkLkGCvJnf02ndkO5io7158acxrb4FyzgumB41i8yfqyRL U2Ug== X-Gm-Message-State: APjAAAUAjsqjsI9k1PRFy+lVOqNQAwoKlIYSxYbuFgfk2tPEJRWNFTuo lb9Fd8mWu+goEAJ593p+pfSlHzhO X-Google-Smtp-Source: APXvYqxa214+ih633oh3+kB0Y3aepCLTtQ6+9GVfLJ9LN38tcSVzFg0g7zIgthHW4cPmpcMvvmzR/A== X-Received: by 2002:a17:902:7448:: with SMTP id e8mr6705841plt.85.1565159091917; Tue, 06 Aug 2019 23:24:51 -0700 (PDT) Received: from wafer.ozlabs.ibm.com.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id n98sm21573054pjc.26.2019.08.06.23.24.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 06 Aug 2019 23:24:51 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Wed, 7 Aug 2019 16:24:35 +1000 Message-Id: <20190807062435.19780-3-oohall@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190807062435.19780-1-oohall@gmail.com> References: <20190807062435.19780-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 3/3] include/xscom: Use the name EQ rather than EP X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The P9 pervasive spec uses the term "EP" to refer to the combination of an EQ chiplet and its two child EX chiplets. Nothing else seems to use the term EP and in Skiboot all the uses of the XSCOM_ADDR_P9_EP() macro are to translate the address of EQ specific SCOM registers. Change the name of our address calculation macros to match the general terminology to make what it does clearer. Cc: Anju T Sudhakar Signed-off-by: Oliver O'Halloran --- hw/imc.c | 12 ++++++------ include/xscom.h | 14 +++++++++----- 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index 46b93001a597..ca06f3c36679 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -699,7 +699,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, pdbar_scom_index[port_id]), (u64)(CORE_IMC_PDBAR_MASK & addr))) { prerror("error in xscom_write for pdbar\n"); @@ -710,7 +710,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) { struct proc_chip *chip = get_chip(c->chip_id); - scoms = XSCOM_ADDR_P9_EP(phys_core_id, + scoms = XSCOM_ADDR_P9_EQ(phys_core_id, pdbar_scom_index[port_id]); ret = stop_api_init(chip, phys_core_id, scoms, (u64)(CORE_IMC_PDBAR_MASK & addr), @@ -743,7 +743,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu } if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm mode\n"); @@ -779,7 +779,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu } } if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, htm_scom_index[port_id]), + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_DISABLE)) { prerror("IMC-trace: error in xscom_write for htm mode\n"); return OPAL_HARDWARE; @@ -845,7 +845,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) * to count with the previous initialization. */ if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64)CORE_IMC_HTM_MODE_ENABLE)) { prerror("IMC OPAL_start: error in xscom_write for htm_mode\n"); @@ -905,7 +905,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) * bits 4-9 of the HTM_MODE scom port. */ if (xscom_write(c->chip_id, - XSCOM_ADDR_P9_EP(phys_core_id, + XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]), (u64) CORE_IMC_HTM_MODE_DISABLE)) { prerror("error in xscom_write for htm_mode\n"); diff --git a/include/xscom.h b/include/xscom.h index 051b7c01d0bc..8a466d567a8f 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -112,17 +112,21 @@ * Additional useful definitions for P9 */ -/* An EQ is a quad (also named an EP) */ -#define XSCOM_ADDR_P9_EP(core, addr) \ +/* + * An EQ is a quad. The Pervasive spec also uses the term "EP" + * to refer to an EQ and it's two child EX chiplets, but + * nothing else does + */ +#define XSCOM_ADDR_P9_EQ(core, addr) \ (((((core) & 0x1c) + 0x40) << 22) | (addr)) -#define XSCOM_ADDR_P9_EP_SLAVE(core, addr) \ - XSCOM_ADDR_P9_EP(core, (addr) | 0xf0000) +#define XSCOM_ADDR_P9_EQ_SLAVE(core, addr) \ + XSCOM_ADDR_P9_EQ(core, (addr) | 0xf0000) /* An EX is a pair of cores. They are accessed via their corresponding EQs * with bit 0x400 indicating which of the 2 EX to address */ #define XSCOM_ADDR_P9_EX(core, addr) \ - (XSCOM_ADDR_P9_EP(core, addr | (((core) & 2) << 9))) + (XSCOM_ADDR_P9_EQ(core, addr | (((core) & 2) << 9))) /* An EC is an individual core and has its own XSCOM addressing */ #define XSCOM_ADDR_P9_EC(core, addr) \