diff mbox series

[3/3] include/xscom: Use the name EQ rather than EP

Message ID 20190807062435.19780-3-oohall@gmail.com
State Accepted
Headers show
Series [1/3] include/xscom: Remove duplicate p8 definitions | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (0e1db80c70477d89a73c7f2a1a7e19c7d8292c5f)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Oliver O'Halloran Aug. 7, 2019, 6:24 a.m. UTC 
The P9 pervasive spec uses the term "EP" to refer to the combination of
an EQ chiplet and its two child EX chiplets. Nothing else seems to use
the term EP and in Skiboot all the uses of the XSCOM_ADDR_P9_EP() macro
are to translate the address of EQ specific SCOM registers.

Change the name of our address calculation macros to match the general
terminology to make what it does clearer.

Cc: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
---
 hw/imc.c        | 12 ++++++------
 include/xscom.h | 14 +++++++++-----
 2 files changed, 15 insertions(+), 11 deletions(-)
diff mbox series

Patch

diff --git a/hw/imc.c b/hw/imc.c
index 46b93001a597..ca06f3c36679 100644
--- a/hw/imc.c
+++ b/hw/imc.c
@@ -699,7 +699,7 @@  static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu
 
 
 		 if (xscom_write(c->chip_id,
-				XSCOM_ADDR_P9_EP(phys_core_id,
+				XSCOM_ADDR_P9_EQ(phys_core_id,
 						pdbar_scom_index[port_id]),
 				(u64)(CORE_IMC_PDBAR_MASK & addr))) {
 			prerror("error in xscom_write for pdbar\n");
@@ -710,7 +710,7 @@  static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu
 			if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) {
 				struct proc_chip *chip = get_chip(c->chip_id);
 
-				scoms = XSCOM_ADDR_P9_EP(phys_core_id,
+				scoms = XSCOM_ADDR_P9_EQ(phys_core_id,
 						pdbar_scom_index[port_id]);
 				ret = stop_api_init(chip, phys_core_id, scoms,
 						(u64)(CORE_IMC_PDBAR_MASK & addr),
@@ -743,7 +743,7 @@  static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu
 		}
 
 		if (xscom_write(c->chip_id,
-				XSCOM_ADDR_P9_EP(phys_core_id,
+				XSCOM_ADDR_P9_EQ(phys_core_id,
 						htm_scom_index[port_id]),
 				(u64)CORE_IMC_HTM_MODE_DISABLE)) {
 			prerror("error in xscom_write for htm mode\n");
@@ -779,7 +779,7 @@  static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu
 			}
 		}
 		if (xscom_write(c->chip_id,
-			XSCOM_ADDR_P9_EP(phys_core_id, htm_scom_index[port_id]),
+			XSCOM_ADDR_P9_EQ(phys_core_id, htm_scom_index[port_id]),
 					(u64)CORE_IMC_HTM_MODE_DISABLE)) {
 				prerror("IMC-trace: error in xscom_write for htm mode\n");
 				return OPAL_HARDWARE;
@@ -845,7 +845,7 @@  static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir)
 		 * to count with the previous initialization.
 		 */
 		if (xscom_write(c->chip_id,
-				XSCOM_ADDR_P9_EP(phys_core_id,
+				XSCOM_ADDR_P9_EQ(phys_core_id,
 						htm_scom_index[port_id]),
 				(u64)CORE_IMC_HTM_MODE_ENABLE)) {
 			prerror("IMC OPAL_start: error in xscom_write for htm_mode\n");
@@ -905,7 +905,7 @@  static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir)
 		 * bits 4-9 of the HTM_MODE scom port.
 		 */
 		if (xscom_write(c->chip_id,
-				XSCOM_ADDR_P9_EP(phys_core_id,
+				XSCOM_ADDR_P9_EQ(phys_core_id,
 						htm_scom_index[port_id]),
 				(u64) CORE_IMC_HTM_MODE_DISABLE)) {
 			prerror("error in xscom_write for htm_mode\n");
diff --git a/include/xscom.h b/include/xscom.h
index 051b7c01d0bc..8a466d567a8f 100644
--- a/include/xscom.h
+++ b/include/xscom.h
@@ -112,17 +112,21 @@ 
  * Additional useful definitions for P9
  */
 
-/* An EQ is a quad (also named an EP) */
-#define XSCOM_ADDR_P9_EP(core, addr) \
+/*
+ * An EQ is a quad. The Pervasive spec also uses the term "EP"
+ * to refer to an EQ and it's two child EX chiplets, but
+ * nothing else does
+ */
+#define XSCOM_ADDR_P9_EQ(core, addr) \
 	(((((core) & 0x1c) + 0x40) << 22) | (addr))
-#define XSCOM_ADDR_P9_EP_SLAVE(core, addr) \
-	XSCOM_ADDR_P9_EP(core, (addr) | 0xf0000)
+#define XSCOM_ADDR_P9_EQ_SLAVE(core, addr) \
+	XSCOM_ADDR_P9_EQ(core, (addr) | 0xf0000)
 
 /* An EX is a pair of cores. They are accessed via their corresponding EQs
  * with bit 0x400 indicating which of the 2 EX to address
  */
 #define XSCOM_ADDR_P9_EX(core, addr) \
-	(XSCOM_ADDR_P9_EP(core, addr | (((core) & 2) << 9)))
+	(XSCOM_ADDR_P9_EQ(core, addr | (((core) & 2) << 9)))
 
 /* An EC is an individual core and has its own XSCOM addressing */
 #define XSCOM_ADDR_P9_EC(core, addr) \