From patchwork Thu Jul 18 01:54:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1133493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45pxz20YF1z9sBt for ; Thu, 18 Jul 2019 11:54:54 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cvC6lyO3"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45pxz16Kx1zDqTV for ; Thu, 18 Jul 2019 11:54:53 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cvC6lyO3"; dkim-atps=neutral Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45pxyt0mfXzDqSZ for ; Thu, 18 Jul 2019 11:54:45 +1000 (AEST) Received: by mail-pg1-x544.google.com with SMTP id w10so12069005pgj.7 for ; Wed, 17 Jul 2019 18:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GxPLMmb6JOD3sTRm3CS9+nItjTSLeWUx22qU71HEOgo=; b=cvC6lyO3hX6KEo2hlHP6MQfhfF4u8FG4zFz3yeJ9sv8zofsDR4Ni06ZnvBJmPqTgZj H4mTiJ+FPShAP/+ckC8gS/hRFlGJoMFBV7qT5TfxS1yyGsOcMAvsjmxQ1Ttjh7mDF8hM h2cS9NGUhzo8j+4mrprdVslO+/s3EcRinY8uqP9n8LD9p+eZrmgtNSRR9eBxxv8ncD97 mexnxB3h8IRt4rGnFiqBQGy7Mt4GEwgekReOSS+T1ZuEjb0bBFqTbeGrkAhHT7+6zwtd 7Kd4uWGKQEJUtbpMX905rTu9WFvLIBDV77eKgrNqG0CjOYltaXcLNNaJU7Ev+qwmbV6p nOFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=GxPLMmb6JOD3sTRm3CS9+nItjTSLeWUx22qU71HEOgo=; b=GiAMqpuff/cP7VocUvvPCvQ2/wGH+lTZVH1PHRHLcNNg0CwUIhNSfLGVcsc1HbRHd0 Ww9jvuSF87/+CK4iScMz3IKC7UT07r6wLvTX2hMpsYML3vzCRLMDL9PCXFFHsZ0Y/4wC 6ZZjAwprsPNKAlXh2XhOkm6zQLsHd2NBm5EzCZyadRIDX6ayoxj00ODeZpB8YPQnGROU JuBPSeTW9o8o0YtheeUuCwYfM7XzjnIQe336NeZFqd7gxpeii5cvMw6jIBcQG96kvcqI mQg1QR8wpbT/DhzFlpsokKrDx/ezImZE6lS6N4YDwtHJJsR6l//47ciNsBvWcyVB96wX FaxQ== X-Gm-Message-State: APjAAAWB77nUj3bhQlsbliNEFuYFqXwXVhjL6gIkIbyng8i/OTe77DpL 3Fh33OmbYMKGdmQroITmLIw1O67Z X-Google-Smtp-Source: APXvYqzxhKp8a2lLxmBIzyPjM8akpovedDOb3YXqzcKL3BI4NDLSEgSzW7Ciz4ZIchDDpyTK91esKw== X-Received: by 2002:a63:381d:: with SMTP id f29mr45667586pga.101.1563414879197; Wed, 17 Jul 2019 18:54:39 -0700 (PDT) Received: from bobo.local0.net ([203.220.8.141]) by smtp.gmail.com with ESMTPSA id 81sm40799423pfx.111.2019.07.17.18.54.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 17 Jul 2019 18:54:38 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 18 Jul 2019 11:54:27 +1000 Message-Id: <20190718015427.25567-1-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Subject: [Skiboot] [PATCH] external/mambo: mce injection step over uninteresting states X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The MCE injection/step test skips over MSR[RI]=0, as it's an "uninteresting" state (leads to die/crash). MSR[ME]=0 is similarly uninteresting. MSR[PR]=1 is not interesting to do fine grained injection because all MSR[PR]=1 states are much the same, from machine check point of view, so skip this too. MSR[EE]=1 is often not very interesting, because the kernel is well tested for interrupt re-entrancy by asynchronous interrupts in these states. However it is possible for the machine check handler to have bugs in MSR[EE]=1, so make it optional to disable this state. This makes injection testing easier and faster. This patch also adds a bit more output to exc_mce, including printing the initial 0x200 instruction details which makes things much less confusing when stepping through a machine check. Signed-off-by: Nicholas Piggin --- external/mambo/mambo_utils.tcl | 67 +++++++++++++++++++++++----------- 1 file changed, 46 insertions(+), 21 deletions(-) diff --git a/external/mambo/mambo_utils.tcl b/external/mambo/mambo_utils.tcl index 1defe95ad..0518fe81c 100644 --- a/external/mambo/mambo_utils.tcl +++ b/external/mambo/mambo_utils.tcl @@ -562,6 +562,9 @@ proc exc_sreset { } { upvar #0 target_c c upvar #0 target_p p + set pc [mysim cpu $p:$c:$t display spr pc] + puts "\[$p:$c:$t\]: $pc injecting SRESET" + # In case of recoverable MCE, idle wakeup always sets RI, others get # RI from current environment. For unrecoverable, RI would always be # clear by hardware. @@ -601,6 +604,8 @@ proc exc_sreset { } { if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x104 ] } { sreset_trigger } + + ipc $t $c $p } proc mce_trigger { args } { @@ -642,7 +647,8 @@ proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } { upvar #0 target_c c upvar #0 target_p p -# puts "INJECTING MCE" + set pc [mysim cpu $p:$c:$t display spr pc] + puts "\[$p:$c:$t\]: $pc injecting MCE" # In case of recoverable MCE, idle wakeup always sets RI, others get # RI from current environment. For unrecoverable, RI would always be @@ -698,6 +704,8 @@ proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } { if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x204 ] } { mce_trigger } + + ipc $t $c $p } set R1 0 @@ -713,7 +721,7 @@ proc stop_stack_match { args } { set r1 [mysim cpu $p:$c:$t display gpr 1] if { $R1 == $r1 } { simstop - ipca + ipc $t $c $p } } @@ -754,8 +762,16 @@ proc inject_mce_step { {nr 1} } { } } -# inject if RI is set and step over one instruction, and repeat. -proc inject_mce_step_ri { {nr 1} } { +# inject if ME and RI is set and PR is clear, step over the MCE to the next +# instruction, and repeat. +# Optionally skip the MCE if EE is set, as it's less interesting and allows +# faster test coverage (however some interesting cases can be missed here, +# e.g., user copies that modify AMR). +# +# This also contains some logic to avoid always killing reservations and +# halting progress, but it does not always work so sometimes you get caught +# in a reservation loop and have to step out of it manually. +proc inject_mce_step_skip { {nr 1} {skip_ee 0} } { upvar #0 target_t t upvar #0 target_c c upvar #0 target_p p @@ -765,29 +781,38 @@ proc inject_mce_step_ri { {nr 1} } { set reserve_counter 0 for { set i 0 } { $i < $nr } { incr i 1 } { - if { [expr [mysim cpu $p:$c:$t display spr msr] & 0x2] } { - # inject_mce - if { [mysim cpu $p:$c:$t display reservation] in { "none" } } { + # Skip the injection if MSR[RI]=0 or MSR[ME]=0 or MSR[PR]=1 + if { [ expr {!([p msr] & 0x2) || !([p msr] & 0x1000) || ([p msr] & 0x4000) } ] } { + mysim step 1 + continue + } + + if { $skip_ee && ([p msr] & 0x8000)} { + mysim step 1 + continue + } + + # inject_mce + if { [mysim cpu $p:$c:$t display reservation] in { "none" } } { + inject_mce + mysim cpu $p:$c:$t set reservation none + if { $reserve_inject_skip } { + set reserve_inject 1 + set reserve_inject_skip 0 + } + } else { + if { $reserve_inject } { inject_mce mysim cpu $p:$c:$t set reservation none - if { $reserve_inject_skip } { - set reserve_inject 1 - set reserve_inject_skip 0 - } + set reserve_inject 0 } else { - if { $reserve_inject } { - inject_mce + set reserve_inject_skip 1 + set reserve_counter [ expr $reserve_counter + 1 ] + if { $reserve_counter > 30 } { mysim cpu $p:$c:$t set reservation none - set reserve_inject 0 - } else { - set reserve_inject_skip 1 - set reserve_counter [ expr $reserve_counter + 1 ] - if { $reserve_counter > 30 } { - mysim cpu $p:$c:$t set reservation none - } } } } - s + mysim step 1 } }