@@ -5,6 +5,6 @@ FSP_OBJS += fsp-surveillance.o fsp-codeupdate.o fsp-sensor.o
FSP_OBJS += fsp-diag.o fsp-leds.o fsp-mem-err.o fsp-op-panel.o
FSP_OBJS += fsp-elog-read.o fsp-elog-write.o fsp-epow.o fsp-dpo.o
FSP_OBJS += fsp-dump.o fsp-mdst-table.o fsp-chiptod.o fsp-ipmi.o
-FSP_OBJS += fsp-attn.o fsp-occ.o
+FSP_OBJS += fsp-attn.o fsp-occ.o fsp-psi.o
FSP = hw/fsp/built-in.a
$(FSP): $(FSP_OBJS:%=hw/fsp/%)
new file mode 100644
@@ -0,0 +1,97 @@
+/* Copyright 2013-2014 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <io.h>
+#include <psi.h>
+#include <lock.h>
+#include <fsp.h>
+
+static void psi_tce_enable(struct psi *psi, bool enable)
+{
+ void *addr;
+ u64 val;
+
+ switch (proc_gen) {
+ case proc_gen_p8:
+ case proc_gen_p9:
+ addr = psi->regs + PSIHB_PHBSCR;
+ break;
+ default:
+ prerror("%s: Unknown CPU type\n", __func__);
+ return;
+ }
+
+ val = in_be64(addr);
+ if (enable)
+ val |= PSIHB_CR_TCE_ENABLE;
+ else
+ val &= ~PSIHB_CR_TCE_ENABLE;
+ out_be64(addr, val);
+}
+
+/*
+ * Configure the PSI interface for communicating with
+ * an FSP, such as enabling the TCEs, FSP commands,
+ * etc...
+ */
+void psi_init_for_fsp(struct psi *psi)
+{
+ uint64_t reg;
+ bool enable_tce = true;
+
+ lock(&psi_lock);
+
+ /* Disable and setup TCE base address */
+ psi_tce_enable(psi, false);
+
+ switch (proc_gen) {
+ case proc_gen_p8:
+ case proc_gen_p9:
+ out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE |
+ PSIHB_TAR_256K_ENTRIES);
+ break;
+ default:
+ enable_tce = false;
+ };
+
+ /* Enable various other configuration register bits based
+ * on what pHyp does. We keep interrupts disabled until
+ * after the mailbox has been properly configured. We assume
+ * basic stuff such as PSI link enable is already there.
+ *
+ * - FSP CMD Enable
+ * - FSP MMIO Enable
+ * - TCE Enable
+ * - Error response enable
+ *
+ * Clear all other error bits
+ */
+ if (!psi->active) {
+ prerror("PSI: psi_init_for_fsp() called on inactive link!\n");
+ unlock(&psi_lock);
+ return;
+ }
+
+ reg = in_be64(psi->regs + PSIHB_CR);
+ reg |= PSIHB_CR_FSP_CMD_ENABLE;
+ reg |= PSIHB_CR_FSP_MMIO_ENABLE;
+ reg |= PSIHB_CR_FSP_ERR_RSP_ENABLE;
+ reg &= ~0x00000000ffffffffull;
+ out_be64(psi->regs + PSIHB_CR, reg);
+ psi_tce_enable(psi, enable_tce);
+
+ unlock(&psi_lock);
+}
@@ -45,7 +45,7 @@ static bool psi_ext_irq_policy = EXTERNAL_IRQ_POLICY_LINUX;
static void psi_activate_phb(struct psi *psi);
-static struct lock psi_lock = LOCK_UNLOCKED;
+struct lock psi_lock = LOCK_UNLOCKED;
DEFINE_LOG_ENTRY(OPAL_RC_PSI_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_PSI,
OPAL_PLATFORM_FIRMWARE,
@@ -199,7 +199,8 @@ static void psi_link_poll(void *data __unused)
psi_activate_phb(psi);
psi_set_link_polling(false);
unlock(&psi_lock);
- fsp_reinit_fsp();
+ if (platform.psi && platform.psi->link_established)
+ platform.psi->link_established();
return;
}
}
@@ -333,14 +334,14 @@ static void psihb_interrupt(struct irq_source *is, uint32_t isn __unused)
*/
if (!psi->active)
psi_spurious_fsp_irq(psi);
- else
- fsp_interrupt();
+ else {
+ if (platform.psi && platform.psi->fsp_interrupt)
+ platform.psi->fsp_interrupt();
+ }
}
- /* Poll the console buffers on any interrupt since we don't
- * get send notifications
- */
- fsp_console_poll(NULL);
+ if (platform.psi && platform.psi->psihb_interrupt)
+ platform.psi->psihb_interrupt();
}
@@ -627,83 +628,6 @@ static const struct irq_source_ops psi_p9_irq_ops = {
.name = psi_p9_irq_name,
};
-static void psi_tce_enable(struct psi *psi, bool enable)
-{
- void *addr;
- u64 val;
-
- switch (proc_gen) {
- case proc_gen_p8:
- case proc_gen_p9:
- addr = psi->regs + PSIHB_PHBSCR;
- break;
- default:
- prerror("%s: Unknown CPU type\n", __func__);
- return;
- }
-
- val = in_be64(addr);
- if (enable)
- val |= PSIHB_CR_TCE_ENABLE;
- else
- val &= ~PSIHB_CR_TCE_ENABLE;
- out_be64(addr, val);
-}
-
-/*
- * Configure the PSI interface for communicating with
- * an FSP, such as enabling the TCEs, FSP commands,
- * etc...
- */
-void psi_init_for_fsp(struct psi *psi)
-{
- uint64_t reg;
- bool enable_tce = true;
-
- lock(&psi_lock);
-
- /* Disable and setup TCE base address */
- psi_tce_enable(psi, false);
-
- switch (proc_gen) {
- case proc_gen_p8:
- case proc_gen_p9:
- out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE |
- PSIHB_TAR_256K_ENTRIES);
- break;
- default:
- enable_tce = false;
- };
-
- /* Enable various other configuration register bits based
- * on what pHyp does. We keep interrupts disabled until
- * after the mailbox has been properly configured. We assume
- * basic stuff such as PSI link enable is already there.
- *
- * - FSP CMD Enable
- * - FSP MMIO Enable
- * - TCE Enable
- * - Error response enable
- *
- * Clear all other error bits
- */
- if (!psi->active) {
- prerror("PSI: psi_init_for_fsp() called on inactive link!\n");
- unlock(&psi_lock);
- return;
- }
-
- reg = in_be64(psi->regs + PSIHB_CR);
- reg |= PSIHB_CR_FSP_CMD_ENABLE;
- reg |= PSIHB_CR_FSP_MMIO_ENABLE;
- reg |= PSIHB_CR_FSP_ERR_RSP_ENABLE;
- reg &= ~0x00000000ffffffffull;
- out_be64(psi->regs + PSIHB_CR, reg);
- psi_tce_enable(psi, enable_tce);
-
- unlock(&psi_lock);
-}
-
void psi_set_external_irq_policy(bool policy)
{
psi_ext_irq_policy = policy;
@@ -79,6 +79,16 @@ struct platform_ocapi {
struct dt_node;
+/*
+ * Just for FSP platforms, allows us to partly decouple
+ * FSP specific code from core code.
+ */
+struct platform_psi {
+ void (*psihb_interrupt)(void);
+ void (*link_established)(void);
+ void (*fsp_interrupt)(void);
+};
+
/*
* Each platform can provide a set of hooks
* that can affect the generic code
@@ -93,6 +103,11 @@ struct platform {
*/
const struct bmc_platform *bmc;
+ /*
+ * PSI handling code. FSP specific.
+ */
+ const struct platform_psi *psi;
+
/* OpenCAPI platform-specific I2C information */
const struct platform_ocapi *ocapi;
@@ -273,6 +273,6 @@ extern void psi_fsp_link_in_use(struct psi *psi);
#define EXTERNAL_IRQ_POLICY_SKIBOOT true
extern void psi_set_external_irq_policy(bool policy);
-
+extern struct lock psi_lock;
#endif /* __PSI_H */
@@ -261,3 +261,17 @@ int __attrconst fsp_heartbeat_time(void)
/* Same as core/timer.c HEARTBEAT_DEFAULT_MS * 10 */
return 200 * 10;
}
+
+static void fsp_psihb_interrupt(void)
+{
+ /* Poll the console buffers on any interrupt since we don't
+ * get send notifications
+ */
+ fsp_console_poll(NULL);
+}
+
+struct platform_psi fsp_platform_psi = {
+ .psihb_interrupt = fsp_psihb_interrupt,
+ .link_established = fsp_reinit_fsp,
+ .fsp_interrupt = fsp_interrupt,
+};
@@ -209,6 +209,7 @@ static void firenze_init(void)
DECLARE_PLATFORM(firenze) = {
.name = "Firenze",
+ .psi = &fsp_platform_psi,
.probe = firenze_probe,
.init = firenze_init,
.fast_reboot_init = fsp_console_reset,
@@ -50,5 +50,6 @@ void vpd_preload(struct dt_node *hub_node);
/* Platform heartbeat time */
int fsp_heartbeat_time(void);
+extern struct platform_psi fsp_platform_psi;
#endif /* __IBM_FSP_COMMON_H */
@@ -71,6 +71,7 @@ static void zz_init(void)
DECLARE_PLATFORM(zz) = {
.name = "ZZ",
+ .psi = &fsp_platform_psi,
.probe = zz_probe,
.init = zz_init,
.fast_reboot_init = fsp_console_reset,
Signed-off-by: Stewart Smith <stewart@linux.ibm.com> --- hw/fsp/Makefile.inc | 2 +- hw/fsp/fsp-psi.c | 97 +++++++++++++++++++++++++++++++++++++ hw/psi.c | 94 ++++------------------------------- include/platform.h | 15 ++++++ include/psi.h | 2 +- platforms/ibm-fsp/common.c | 14 ++++++ platforms/ibm-fsp/firenze.c | 1 + platforms/ibm-fsp/ibm-fsp.h | 1 + platforms/ibm-fsp/zz.c | 1 + 9 files changed, 140 insertions(+), 87 deletions(-) create mode 100644 hw/fsp/fsp-psi.c