| Message ID | 20190307024008.8028-1-oohall@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | hw/phb4: Squash the IO bridge window | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (261ca8e779e5138869a45f174caa49be6a274501) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
"Oliver O'Halloran" <oohall@gmail.com> writes: > The PCI-PCI bridge spec says that bridges that implement an IO window > should hardcode the IO base and limit registers to zero. > Unfortunately, these registers only define the upper bits of the IO > window and the low bits are assumed to be 0 for the base and 1 for the > limit address. As a result, setting both to zero can be mis-interpreted > as a 4K IO window. > > This patch fixes the problem the same way PHB3 does. It sets the IO base > and limit values to 0xf000 and 0x1000 respectively which most software > interprets as a disabled window. > > lspci before patch: > > 0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode]) > I/O behind bridge: 00000000-00000fff > > lspci after patch: > > 0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode]) > I/O behind bridge: None > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> > --- > hw/phb4.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Merged to master as of b507209d22669ab0a2ad49822d11b2cbb08c49f1
diff --git a/hw/phb4.c b/hw/phb4.c index ffdb01632fd2..4e77dd8e58e8 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -319,6 +319,14 @@ static int64_t phb4_rc_read(struct phb4 *p, uint32_t offset, uint8_t sz, oval = in_le32(p->regs + PHB_RC_CONFIG_BASE + reg); } } + + /* Apply any post-read fixups */ + switch (reg) { + case PCI_CFG_IO_BASE: + oval |= 0x01f1; /* Set IO base < limit to disable the window */ + break; + } + switch (sz) { case 1: offset &= 3;
The PCI-PCI bridge spec says that bridges that implement an IO window should hardcode the IO base and limit registers to zero. Unfortunately, these registers only define the upper bits of the IO window and the low bits are assumed to be 0 for the base and 1 for the limit address. As a result, setting both to zero can be mis-interpreted as a 4K IO window. This patch fixes the problem the same way PHB3 does. It sets the IO base and limit values to 0xf000 and 0x1000 respectively which most software interprets as a disabled window. lspci before patch: 0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode]) I/O behind bridge: 00000000-00000fff lspci after patch: 0000:00:00.0 PCI bridge: IBM Device 04c1 (prog-if 00 [Normal decode]) I/O behind bridge: None Signed-off-by: Oliver O'Halloran <oohall@gmail.com> --- hw/phb4.c | 8 ++++++++ 1 file changed, 8 insertions(+)