Message ID | 20180814021926.9818-1-vaibhav@linux.ibm.com |
---|---|
State | Accepted |
Headers | show |
Series | [v2] phb4/capp: Update DMA read engines set in APC_FSM_READ_MASK based on link-width | expand |
Context | Check | Description |
---|---|---|
snowpatch_ozlabs/apply_patch | success | master/apply_patch Successfully applied |
snowpatch_ozlabs/make_check | success | Test make_check on branch master |
Vaibhav Jain <vaibhav@linux.ibm.com> writes: > Commit 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based > on link-width for PEC") update the CAPP init sequence by calculating > the needed STQ/DMA-read engines based on link width and populating it > in XPEC_NEST_CAPP_CNTL register. This however needs to be synchronized > with the value set in CAPP APC FSM Read Machine Mask Register. > > Hence this patch update phb4_init_capp_regs() to calculate the link > width of the stack on PEC2 and populate the same values as previously > populated in PEC CAPP_CNTL register. > > Cc: stable # v5.7+ > Fixes: 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC") > Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> > Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> > --- > Change-log: > > v2 -> Suffixed the constants with 'ULL' [Andrew] > --- > hw/phb4.c | 22 ++++++++++++++++++---- > 1 file changed, 18 insertions(+), 4 deletions(-) Thanks, merged to master as of ef9caad57e59ffc1a9ee44d38a161f624993b67b and backported to 6.0.x as of 9bcde78b4e83ef75bd0a6a5a4c3c5311891ae516
diff --git a/hw/phb4.c b/hw/phb4.c index 5e07e2bc..707ef2ee 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3948,10 +3948,24 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) xscom_write(p->chip_id, XPT_FSM_RMM + offset, reg); } if (p->index == CAPP1_PHB_INDEX) { - /* Set 30 Read machines for CAPP Minus 20-27 for DMA */ - reg = 0xFFFFF00E00000000; - if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) - reg = 0xF000000000000000; + + if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) { + reg = 0xF000000000000000ULL; + } else { + /* Check if PEC is in x8 or x16 mode */ + xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, ®); + if ((reg & XPEC_PCI2_IOVALID_MASK) == + XPEC_PCI2_IOVALID_X16) + /* 0-47 (Read machines) are available for + * capp use + */ + reg = 0x0000FFFFFFFFFFFFULL; + else + /* Set 30 Read machines for CAPP Minus + * 20-27 for DMA + */ + reg = 0xFFFFF00E00000000ULL; + } xscom_write(p->chip_id, APC_FSM_READ_MASK + offset, reg); xscom_write(p->chip_id, XPT_FSM_RMM + offset, reg); }