From patchwork Mon Jun 25 01:40:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Donnellan X-Patchwork-Id: 934024 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41DX1h6SXJz9ryk for ; Mon, 25 Jun 2018 11:40:40 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41DX1h5DRQzF18l for ; Mon, 25 Jun 2018 11:40:40 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=au1.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=andrew.donnellan@au1.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41DX1W2Y0PzF15L for ; Mon, 25 Jun 2018 11:40:31 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w5P1d58i048915 for ; Sun, 24 Jun 2018 21:40:28 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jt31q6xm3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Jun 2018 21:40:28 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 25 Jun 2018 02:40:23 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w5P1eNue32964738 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Jun 2018 01:40:23 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7E0DE11C05B; Mon, 25 Jun 2018 02:40:18 +0100 (BST) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAD0811C04A; Mon, 25 Jun 2018 02:40:17 +0100 (BST) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 25 Jun 2018 02:40:17 +0100 (BST) Received: from intelligence.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 36489A021D; Mon, 25 Jun 2018 11:40:19 +1000 (AEST) From: Andrew Donnellan To: skiboot@lists.ozlabs.org Date: Mon, 25 Jun 2018 11:40:03 +1000 X-Mailer: git-send-email 2.11.0 X-TM-AS-GCONF: 00 x-cbid: 18062501-0020-0000-0000-0000029E7591 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18062501-0021-0000-0000-000020EAE317 Message-Id: <20180625014003.11561-1-andrew.donnellan@au1.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-24_14:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=3 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1806250018 Subject: [Skiboot] [PATCH v2] hw/npu2, core/hmi: Use NPU instead of NPU2 as log message prefix X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The NPU2{DBG,INF,ERR} macros use "NPU%d" as a prefix to identify messages relating to a particular NPU. It's slightly confusing to have per-NPU messages prefixed with "NPU0" or "NPU1" and NPU-generic messages prefixed with "NPU2". On some future system we could potentially have a NPU #2 in which case it'd be really confusing. Use NPU rather than NPU2 for NPU-generic log messages. There's no risk of confusion with the original npu.c code since that's only for P8. Signed-off-by: Andrew Donnellan Acked-by: Reza Arbab --- v1->v2: - Change messages in core/hmi.c as well (thanks Reza) --- core/hmi.c | 6 +++--- hw/npu2.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 3bbdb2a3470a..e6fed405254b 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -694,9 +694,9 @@ static void find_npu2_checkstop_reason(int flat_chip_id, loc = chip_loc_code(flat_chip_id); if (!loc) loc = "Not Available"; - prlog(PR_ERR, "NPU2: [Loc: %s] P:%d FIR#%d FIR 0x%016llx mask 0x%016llx\n", + prlog(PR_ERR, "NPU: [Loc: %s] P:%d FIR#%d FIR 0x%016llx mask 0x%016llx\n", loc, flat_chip_id, i, npu2_fir, npu2_fir_mask); - prlog(PR_ERR, "NPU2: [Loc: %s] P:%d ACTION0 0x%016llx, ACTION1 0x%016llx\n", + prlog(PR_ERR, "NPU: [Loc: %s] P:%d ACTION0 0x%016llx, ACTION1 0x%016llx\n", loc, flat_chip_id, npu2_fir_action0, npu2_fir_action1); total_errors++; } @@ -718,7 +718,7 @@ static void find_npu2_checkstop_reason(int flat_chip_id, if (npu2_hmi_verbose) { _xscom_lock(); - dump_scoms(flat_chip_id, "NPU2", npu2_scom_dump, loc); + dump_scoms(flat_chip_id, "NPU", npu2_scom_dump, loc); _xscom_unlock(); prlog(PR_ERR, " _________________________ \n"); prlog(PR_ERR, "< It's Driver Debug time! >\n"); diff --git a/hw/npu2.c b/hw/npu2.c index 3ed089fc6f26..c351404ac285 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -650,7 +650,7 @@ static int npu2_dn_fixup(struct phb *phb, * @fwts-advice No GPU/NPU2 slot information was found. * NVLink2 functionality will not work. */ - prlog(PR_ERR, "NPU2: Cannot find GPU slot information\n"); + prlog(PR_ERR, "NPU: Cannot find GPU slot information\n"); return 0; } dt_add_property_string(pd->dn, "ibm,loc-code", label); @@ -1354,7 +1354,7 @@ static void npu2_probe_phb(struct dt_node *dn) if (dt_find_compatible_node(dn, NULL, "ibm,npu-link-opencapi")) { /* Die if there's also an NVLink link */ assert(!dt_find_compatible_node(dn, NULL, "ibm,npu-link")); - prlog(PR_INFO, "NPU2: OpenCAPI link configuration detected, " + prlog(PR_INFO, "NPU: OpenCAPI link configuration detected, " "not initialising NVLink\n"); return; } @@ -1365,7 +1365,7 @@ static void npu2_probe_phb(struct dt_node *dn) proc_chip = get_chip(gcid); assert(proc_chip); if ((proc_chip->ec_level & 0xf0) > 0x20) { - prerror("NPU2: unsupported ec level on Chip 0x%x!\n", gcid); + prerror("NPU: unsupported ec level on Chip 0x%x!\n", gcid); return; } @@ -1437,7 +1437,7 @@ static void npu2_probe_phb(struct dt_node *dn) index = dt_prop_get_u32(dn, "ibm,npu-index"); phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); links = dt_prop_get_u32(dn, "ibm,npu-links"); - prlog(PR_INFO, "NPU2: Chip %d Found NPU2#%d (%d links) at %s\n", + prlog(PR_INFO, "NPU: Chip %d Found NPU2#%d (%d links) at %s\n", gcid, index, links, path); free(path); @@ -1915,7 +1915,7 @@ static void npu2_setup_irqs(struct npu2 *p) p->base_lsi = xive_alloc_ipi_irqs(p->chip_id, NPU2_N_DL_IRQS, NPU2_N_DL_IRQS_ALIGN); if (p->base_lsi == XIVE_IRQ_ERROR) { - prlog(PR_ERR, "NPU2: Failed to allocate interrupt sources, IRQs for NDL No-stall events will not be available.\n"); + prlog(PR_ERR, "NPU: Failed to allocate interrupt sources, IRQs for NDL No-stall events will not be available.\n"); return; } xive_register_ipi_source(p->base_lsi, NPU2_N_DL_IRQS, p, &npu2_ipi_ops ); @@ -1984,7 +1984,7 @@ static void npu2_create_phb(struct dt_node *dn) * @fwts-advice Firmware probably ran out of memory creating * NPU2 slot. NVLink functionality could be broken. */ - prlog(PR_ERR, "NPU2: Cannot create PHB slot\n"); + prlog(PR_ERR, "NPU: Cannot create PHB slot\n"); } pci_register_phb(&p->phb_nvlink, OPAL_DYNAMIC_PHB_ID); @@ -2004,7 +2004,7 @@ void probe_npu2(void) (chip->type == PROC_CHIP_P9_NIMBUS || chip->type == PROC_CHIP_P9_CUMULUS) && (chip->ec_level & 0xf0) == 0x10) { - prlog(PR_INFO, "NPU2: DD1 not supported\n"); + prlog(PR_INFO, "NPU: DD1 not supported\n"); return; } @@ -2012,7 +2012,7 @@ void probe_npu2(void) zcal = nvram_query("nv_zcal_override"); if (zcal) { nv_zcal_nominal = atoi(zcal); - prlog(PR_WARNING, "NPU2: Using ZCAL impedance override = %d\n", nv_zcal_nominal); + prlog(PR_WARNING, "NPU: Using ZCAL impedance override = %d\n", nv_zcal_nominal); } /* Scan NPU2 XSCOM nodes */