From patchwork Fri Dec 1 12:34:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Philippe Bergheaud X-Patchwork-Id: 843474 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ypDJL4LKSz9t9g for ; Fri, 1 Dec 2017 23:35:30 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ypDJL30XGzDsPH for ; Fri, 1 Dec 2017 23:35:30 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=felix@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ypDHz4WByzDqpV for ; Fri, 1 Dec 2017 23:35:11 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vB1CYSEg111972 for ; Fri, 1 Dec 2017 07:35:09 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ek4p4fkga-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 01 Dec 2017 07:35:07 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 1 Dec 2017 12:35:04 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vB1CZ2Q949938474; Fri, 1 Dec 2017 12:35:02 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A26C7AE070; Fri, 1 Dec 2017 12:28:06 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9A105AE067; Fri, 1 Dec 2017 12:28:06 +0000 (GMT) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 1 Dec 2017 12:28:06 +0000 (GMT) Received: from w541.lab.toulouse-stg.fr.ibm.com (t42p.lab.toulouse-stg.fr.ibm.com [9.101.4.37]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id D61E82202BD; Fri, 1 Dec 2017 13:35:01 +0100 (CET) From: Philippe Bergheaud To: skiboot@lists.ozlabs.org Date: Fri, 1 Dec 2017 13:34:47 +0100 X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17120112-0016-0000-0000-00000507CA49 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17120112-0017-0000-0000-00002843BA38 Message-Id: <20171201123448.3877-1-felix@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-12-01_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1712010154 Subject: [Skiboot] [PATCH v2 1/2] phb4: set PHB CMPM registers for tunneled operations X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: benh@au1.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" P9 supports PCI tunneled operations (atomics and as_notify) that require setting the PHB ASN Compare/Mask register with a 16-bit indication. This register is currently initialized by enable_capi_mode(). But, as tunneled operations may also work in PCI mode, the ASN Compare/Mask register should rather be initialized in phb4_init_ioda3(). This patch also adds "ibm,phb-indications" to the device tree, to tell Linux the values of CAPI, ASN, and NBW indications, when supported. Signed-off-by: Philippe Bergheaud Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com --- Changelog: v2: Do not let Linux choose indication values. Let skiboot tell Linux via the device tree. Initialize the PHB ASN indication in PCI mode. --- hw/phb4.c | 30 ++++++++++++++++++++++-------- include/phb4-regs.h | 4 ++-- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index cfadf59d..94e67e9f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3695,6 +3695,13 @@ static void phb4_init_capp_errors(struct phb4 *p) out_be64(p->regs + 0x0cb0, 0x35777073ff000000ull); } +#define CAPIIND 0x0200 +#define CAPIMASK 0xFE00 +#define ASNIND 0x0400 +#define ASNMASK 0xF7FF +#define NBWIND 0x0300 +#define NBWMASK 0xF700 + /* Power Bus Common Queue Registers * All PBCQ and PBAIB registers are accessed via SCOM * NestBase = 4010C00 for PEC0 @@ -3707,7 +3714,7 @@ static void phb4_init_capp_errors(struct phb4 *p) * Some registers are shared amongst all of the stacks and will only * have 1 copy. Other registers are implemented one per stack. * Registers that are duplicated will have an additional offset - * of “StackBase” so that they have a unique address. + * of 'StackBase' so that they have a unique address. * Stackoffset = 00000040 for Stack0 * = 00000080 for Stack1 * = 000000C0 for Stack2 @@ -3785,16 +3792,13 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, /* * Bit [0:7] XSL_DSNCTL[capiind] - * Init_25 - CAPI Compare/Mask + * Init_26 - CAPI Compare/Mask */ out_be64(p->regs + PHB_CAPI_CMPM, - 0x0200FE0000000000Ull | PHB_CAPI_CMPM_ENABLE); + ((u64)CAPIIND << 48) | + ((u64)CAPIMASK << 32) | PHB_CAPI_CMPM_ENABLE); if (!(p->rev == PHB4_REV_NIMBUS_DD10)) { - /* Init_24 - ASN Compare/Mask */ - out_be64(p->regs + PHB_PBL_ASN_CMPM, - 0x0400FF0000000000Ull | PHB_PBL_ASN_ENABLE); - /* PBCQ Tunnel Bar Register * Write Tunnel register to match PSL TNR register */ @@ -4116,7 +4120,10 @@ static void phb4_init_ioda3(struct phb4 *p) /* See enable_capi_mode() */ /* Init_25 - ASN Compare/Mask */ - /* See enable_capi_mode() */ + if (p->rev != PHB4_REV_NIMBUS_DD10) + out_be64(p->regs + PHB_ASN_CMPM, + ((u64)ASNIND << 48) | + ((u64)ASNMASK << 32) | PHB_ASN_CMPM_ENABLE); /* Init_26 - CAPI Compare/Mask */ /* See enable_capi_mode() */ @@ -4716,6 +4723,13 @@ static void phb4_add_properties(struct phb4 *p) /* Indicate to Linux that CAPP timebase sync is supported */ dt_add_property_string(np, "ibm,capp-timebase-sync", NULL); + + /* Tell Linux Compare/Mask indication values */ + if (p->rev == PHB4_REV_NIMBUS_DD10) + dt_add_property_cells(np, "ibm,phb-indications", CAPIIND, 0, 0); + else + dt_add_property_cells(np, "ibm,phb-indications", CAPIIND, + ASNIND, NBWIND); } static bool phb4_calculate_windows(struct phb4 *p) diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 0d8aa48b..34d822a0 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -71,8 +71,8 @@ #define PHB_PEST_BAR 0x1a8 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8,51) -#define PHB_PBL_ASN_CMPM 0x1C0 -#define PHB_PBL_ASN_ENABLE PPC_BIT(63) +#define PHB_ASN_CMPM 0x1C0 +#define PHB_ASN_CMPM_ENABLE PPC_BIT(63) #define PHB_CAPI_CMPM 0x1C8 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) #define PHB_M64_UPPER_BITS 0x1f0