diff mbox series

[1/2] asm/head: initialize preferred DSCR value

Message ID 20171024114100.13714-2-npiggin@gmail.com
State Accepted
Headers show
Series improve ability to pass SPR defaults to Linux | expand

Commit Message

Nicholas Piggin Oct. 24, 2017, 11:40 a.m. UTC 
POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 asm/head.S          | 22 +++++++++++++++++++---
 include/processor.h |  1 +
 2 files changed, 20 insertions(+), 3 deletions(-)

Comments

Stewart Smith Oct. 31, 2017, 3:40 a.m. UTC | #1 
Nicholas Piggin <npiggin@gmail.com> writes:
> POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  asm/head.S          | 22 +++++++++++++++++++---
>  include/processor.h |  1 +
>  2 files changed, 20 insertions(+), 3 deletions(-)

I've taken this specific single patch as of
90583f437bd6f82e47fac1616c4cab1e0ad84d6c, but as mentioned on (internal)
Slack, the second patch breaks kexec for me on some p9 systems, so we
need to think more on this.

and get better at documenting our whole boot/reboot/kexec flow so we can
at least know which parts we don't like, which parts we can/can't change.
diff mbox series

Patch

diff --git a/asm/head.S b/asm/head.S
index d6b58be9..d82e4e5e 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -782,7 +782,7 @@  init_replicated_sprs:
 	cmpwi	cr0,%r3,PVR_TYPE_P8NVL
 	beq	3f
 	cmpwi	cr0,%r3,PVR_TYPE_P9
-	beq	3f
+	beq	4f
 	/* Unsupported CPU type... what do we do ? */
 	b	9f
 
@@ -792,14 +792,30 @@  init_replicated_sprs:
 	mtspr	SPR_LPCR, %r3
 	sync
 	isync
-	b 9f
+	LOAD_IMM64(%r3,0x0)
+	mtspr	SPR_DSCR,%r3
+	b	9f
+
+3:	/* P8, P8E */
+	/* LPCR: sane value */
+	LOAD_IMM64(%r3,0x0040000000000000)
+	mtspr	SPR_LPCR, %r3
+	sync
+	isync
+	LOAD_IMM64(%r3,0x0)
+	mtspr	SPR_DSCR,%r3
+	b	9f
 
-3:	/* P8, P8E, P9 */
+4:	/* P9 */
 	/* LPCR: sane value */
 	LOAD_IMM64(%r3,0x0040000000000000)
 	mtspr	SPR_LPCR, %r3
 	sync
 	isync
+	/* DSCR: Stride-N Stream Enable */
+	LOAD_IMM64(%r3,0x0000000000000010)
+	mtspr	SPR_DSCR,%r3
+
 9:	blr
 
 	.global enter_nap
diff --git a/include/processor.h b/include/processor.h
index 1f18762a..77110d01 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -44,6 +44,7 @@ 
 #define SPR_PIR_P7_MASK		0x03ff	/* Mask of implemented bits */
 
 /* SPR register definitions */
+#define SPR_DSCR	0x011	/* RW: Data stream control reg */
 #define SPR_DSISR	0x012	/* RW: Data storage interrupt status reg */
 #define SPR_DAR		0x013	/* RW: Data address reg */
 #define SPR_DEC		0x016	/* RW: Decrement Register */