From patchwork Mon Oct 9 04:06:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Smith X-Patchwork-Id: 823064 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y9RWp2CsJz9tY1 for ; Mon, 9 Oct 2017 15:06:46 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3y9RWn72HvzDr4W for ; Mon, 9 Oct 2017 15:06:45 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=stewart@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3y9RWg2VRjzDqv8 for ; Mon, 9 Oct 2017 15:06:38 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9944C7s070982 for ; Mon, 9 Oct 2017 00:06:36 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0b-001b2d01.pphosted.com with ESMTP id 2dfpcn38td-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 09 Oct 2017 00:06:35 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 9 Oct 2017 00:06:32 -0400 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v9946Wi553739550; Mon, 9 Oct 2017 04:06:32 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7463AC043; Mon, 9 Oct 2017 00:07:10 -0400 (EDT) Received: from birb.localdomain (unknown [9.83.3.225]) by b01ledav006.gho.pok.ibm.com (Postfix) with SMTP id E0E9AAC03F; Mon, 9 Oct 2017 00:07:09 -0400 (EDT) Received: by birb.localdomain (Postfix, from userid 1000) id 6270A4EC5FD; Mon, 9 Oct 2017 15:06:25 +1100 (AEDT) From: Stewart Smith To: skiboot@lists.ozlabs.org Date: Mon, 9 Oct 2017 15:06:24 +1100 X-Mailer: git-send-email 2.13.6 X-TM-AS-GCONF: 00 x-cbid: 17100904-0024-0000-0000-000002DEFEBD X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007864; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000235; SDB=6.00928470; UDB=6.00467262; IPR=6.00708743; BA=6.00005627; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017454; XFM=3.00000015; UTC=2017-10-09 04:06:33 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17100904-0025-0000-0000-000045AB8BE7 Message-Id: <20171009040624.9091-1-stewart@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-09_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=3 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710090059 Subject: [Skiboot] [PATCH] pci-iov: free memory across fast-reboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" pci_set_cap needs a callback to free data and we need to call that when we're doing __pci_reset() We also need to free pcrf entries. In the future, __pci_reset() and pci_remove_bus() need to come together to be one canonical place on how to free a PCI device rather than the two we have now. This patch *purely* focuses on the problem of not leaking memory across fast-reboot. Signed-off-by: Stewart Smith --- core/pci-iov.c | 9 ++++++++- core/pci.c | 14 +++++++++++--- include/pci.h | 9 +++++++-- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/core/pci-iov.c b/core/pci-iov.c index 06fc4c6fa1e3..8fecebc1292a 100644 --- a/core/pci-iov.c +++ b/core/pci-iov.c @@ -189,6 +189,13 @@ static void pci_iov_init_VF(struct pci_device *pd, struct pci_device *vf) list_head_init(&vf->children); } +static void pci_free_iov_cap(void *data) +{ + struct pci_iov *iov = data; + free(iov->VFs); + free(iov); +} + void pci_init_iov_cap(struct phb *phb, struct pci_device *pd) { int64_t pos; @@ -254,5 +261,5 @@ void pci_init_iov_cap(struct phb *phb, struct pci_device *pd) iov->pos = pos; iov->enabled = false; pci_iov_update_parameters(iov); - pci_set_cap(pd, PCIECAP_ID_SRIOV, pos, iov, true); + pci_set_cap(pd, PCIECAP_ID_SRIOV, pos, iov, pci_free_iov_cap, true); } diff --git a/core/pci.c b/core/pci.c index b6e7e824a498..0809521f8baf 100644 --- a/core/pci.c +++ b/core/pci.c @@ -162,7 +162,7 @@ static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd) return; } - pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, NULL, false); + pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, NULL, NULL, false); /* * XXX We observe a problem on some PLX switches where one @@ -198,7 +198,7 @@ static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd) pos = pci_find_ecap(phb, pd->bdfn, PCIECAP_ID_AER, NULL); if (pos > 0) - pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, true); + pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, NULL, true); } static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) @@ -207,7 +207,7 @@ static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM); if (pos > 0) - pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, false); + pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, NULL, false); } void pci_init_capabilities(struct phb *phb, struct pci_device *pd) @@ -1651,11 +1651,19 @@ void pci_add_device_nodes(struct phb *phb, static void __pci_reset(struct list_head *list) { struct pci_device *pd; + struct pci_cfg_reg_filter *pcrf; + int i; while ((pd = list_pop(list, struct pci_device, link)) != NULL) { __pci_reset(&pd->children); dt_free(pd->dn); free(pd->slot); + while((pcrf = list_pop(&pd->pcrf, struct pci_cfg_reg_filter, link)) != NULL) { + free(pcrf); + } + for(i=0; i < 64; i++) + if (pd->cap[i].free_func) + pd->cap[i].free_func(pd->cap[i].data); free(pd); } } diff --git a/include/pci.h b/include/pci.h index d75c8d141111..c085b6b867bd 100644 --- a/include/pci.h +++ b/include/pci.h @@ -30,6 +30,7 @@ typedef int64_t (*pci_cfg_reg_func)(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); +typedef void (*pci_cap_free_data_func)(void *data); struct pci_cfg_reg_filter { uint32_t flags; #define PCI_REG_FLAG_READ 0x1 @@ -81,6 +82,7 @@ struct pci_device { struct { uint32_t pos; void *data; + pci_cap_free_data_func free_func; } cap[64]; uint32_t mps; /* Max payload size capability */ @@ -96,17 +98,20 @@ struct pci_device { struct list_node link; }; -static inline void pci_set_cap(struct pci_device *pd, int id, - int pos, void *data, bool ext) +static inline void pci_set_cap(struct pci_device *pd, int id, int pos, + void *data, pci_cap_free_data_func free_func, + bool ext) { if (!ext) { pd->cap_list |= (0x1ul << id); pd->cap[id].pos = pos; pd->cap[id].data = data; + pd->cap[id].free_func = free_func; } else { pd->cap_list |= (0x1ul << (id + 32)); pd->cap[id + 32].pos = pos; pd->cap[id + 32].data = data; + pd->cap[id + 32].free_func = free_func; } }