From patchwork Sun Sep 10 07:33:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWW2sKFz9sQl for ; Sun, 10 Sep 2017 17:35:03 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWW1LWhzDrKk for ; Sun, 10 Sep 2017 17:35:03 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVH26jlzDrcr for ; Sun, 10 Sep 2017 17:33:58 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVak032370; Sun, 10 Sep 2017 02:33:38 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:20 +1000 Message-Id: <20170910073330.25824-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 04/14] xive: Add debug code to check initial cache updates X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds debug code to check that the initial updates of in-memory VPs and EQs via the cache watch and cache scrub facilities has worked properly. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index d6628a09..71280002 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -43,9 +43,11 @@ #ifdef DEBUG #define XIVE_DEBUG_DUPLICATES #define XIVE_PERCPU_LOG +#define XIVE_DEBUG_INIT_CACHE_UPDATES #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG +#undef XIVE_DEBUG_INIT_CACHE_UPDATES #endif /* @@ -2892,12 +2894,57 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_eq *eq_p = xive_get_eq(x_eq, + xs->eq_idx + + XIVE_EMULATION_PRIO); + struct xive_eq eq2; + + assert(eq_p); + eq2 = *eq_p; + if (memcmp(&eq, &eq2, sizeof(eq)) != 0) { + xive_err(x_eq, "EQ update mismatch idx %d\n", + xs->eq_idx); + xive_err(x_eq, "want: %08x %08x %08x %08x\n", + eq.w0, eq.w1, eq.w2, eq.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq.w4, eq.w5, eq.w6, eq.w7); + xive_err(x_eq, "got : %08x %08x %08x %08x\n", + eq2.w0, eq2.w1, eq2.w2, eq2.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq2.w4, eq2.w5, eq2.w6, eq2.w7); + } + } +#endif /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); + + /* Debug code */ +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_vp *vp_p = xive_get_vp(x_vp, xs->vp_idx); + struct xive_vp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(&vp, &vp2, sizeof(vp)) != 0) { + xive_err(x_vp, "VP update mismatch idx %d\n", xs->vp_idx); + xive_err(x_vp, "want: %08x %08x %08x %08x\n", + vp.w0, vp.w1, vp.w2, vp.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp.w4, vp.w5, vp.w6, vp.w7); + xive_err(x_vp, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + } + } +#endif } static void xive_init_cpu_emulation(struct xive_cpu_state *xs,