diff mbox series

[3/7] xive: Ensure pressure relief interrupts are disabled

Message ID 20170909070525.8154-3-benh@kernel.crashing.org
State Superseded
Headers show
Series [1/7] xive: Remove useless memory barriers in VP/EQ inits | expand

Commit Message

Benjamin Herrenschmidt Sept. 9, 2017, 7:05 a.m. UTC 
We don't use them and we hijack the VP field with their
configuration to store the EQ reference, so make sure the
kernel or guest can't turn them back on by doing MMIO
writes to ACK#

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 hw/xive.c      | 2 ++
 include/xive.h | 1 +
 2 files changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/hw/xive.c b/hw/xive.c
index 9148c5f6..d6628a09 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1623,6 +1623,8 @@  static bool xive_config_init(struct xive *x)
 #endif
 	val |= PC_TCTXT_CHIPID_OVERRIDE;
 	val |= PC_TCTXT_CFG_TARGET_EN;
+	/* Disable pressure relief as we hijack the field in the VPs */
+	val &= ~PC_TCTXT_CFG_STORE_ACK;
 	val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id);
 	xive_regw(x, PC_TCTXT_CFG, val);
 	xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);
diff --git a/include/xive.h b/include/xive.h
index 860373c9..70f6499f 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -75,6 +75,7 @@ 
 #define PC_TCTXT_CFG		0x400
 #define  PC_TCTXT_CFG_BLKGRP_EN		PPC_BIT(0)
 #define  PC_TCTXT_CFG_TARGET_EN		PPC_BIT(1)
+#define  PC_TCTXT_CFG_STORE_ACK		PPC_BIT(3)
 #define  PC_TCTXT_CFG_HARD_CHIPID_BLK	PPC_BIT(8)
 #define  PC_TCTXT_CHIPID_OVERRIDE	PPC_BIT(9)
 #define  PC_TCTXT_CHIPID		PPC_BITMASK(12,15)