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[12/16] pci: Add ability to trace timing

Message ID 20170712020655.9499-13-mikey@neuling.org
State Accepted
Headers show

Commit Message

Michael Neuling July 12, 2017, 2:06 a.m. UTC 
PCI link training is responsible for a huge chunk of the skiboot boot
time, so add the ability to trace it waiting in the main state
machine.

Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 core/pci.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/core/pci.c b/core/pci.c
index 907160d11f..49e5bed771 100644
--- a/core/pci.c
+++ b/core/pci.c
@@ -967,6 +967,7 @@  static void pci_reset_phb(void *data)
 	pci_slot_add_flags(slot, PCI_SLOT_FLAG_BOOTUP);
 	rc = slot->ops.freset(slot);
 	while (rc > 0) {
+		PCITRACE(phb, 0, "Waiting %ld ms\n", tb_to_msecs(rc));
 		time_wait(rc);
 		rc = slot->ops.run_sm(slot);
 	}