From patchwork Thu Jun 22 16:22:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 779604 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wtn5P3k9dz9s9Y for ; Fri, 23 Jun 2017 02:26:17 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wtn5P2pkVzDr6R for ; Fri, 23 Jun 2017 02:26:17 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wtn415YvCzDqlw for ; Fri, 23 Jun 2017 02:25:05 +1000 (AEST) Received: from pasglop.austin.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v5MGMaCW024844; Thu, 22 Jun 2017 11:24:19 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 22 Jun 2017 11:22:13 -0500 Message-Id: <20170622162225.26344-12-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170622162225.26344-1-benh@kernel.crashing.org> References: <20170622162225.26344-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 12/24] psi: Switch to ESB mode later X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There's an errata, if we switch to ESB mode before setting up the various ESB mode related registers, a pending interrupts can go wrong. Signed-off-by: Benjamin Herrenschmidt --- hw/psi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/psi.c b/hw/psi.c index c98babf..9da0257 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -826,10 +826,6 @@ static void psi_init_p9_interrupts(struct psi *psi) bool is_p9ndd1; u64 val; - /* Reset irq handling and switch to ESB mode */ - out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); - out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); - /* Grab chip */ chip = get_chip(psi->chip_id); if (!chip) @@ -874,6 +870,10 @@ static void psi_init_p9_interrupts(struct psi *psi) 12, psi->esb_mmio, XIVE_SRC_LSI, psi, &psi_p9_irq_ops); } + + /* Reset irq handling and switch to ESB mode */ + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, PSIHB_IRQ_RESET); + out_be64(psi->regs + PSIHB_INTERRUPT_CONTROL, 0); } static void psi_init_interrupts(struct psi *psi)