From patchwork Thu Jun 22 16:22:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 779603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wtn520mJxz9t1K for ; Fri, 23 Jun 2017 02:25:58 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wtn516J1NzDr4m for ; Fri, 23 Jun 2017 02:25:57 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wtn3r41syzDr57 for ; Fri, 23 Jun 2017 02:24:55 +1000 (AEST) Received: from pasglop.austin.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v5MGMaCV024844; Thu, 22 Jun 2017 11:24:02 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 22 Jun 2017 11:22:12 -0500 Message-Id: <20170622162225.26344-11-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170622162225.26344-1-benh@kernel.crashing.org> References: <20170622162225.26344-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 11/24] lpc: Enable "new" SerIRQ mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" So we don't have to clear the bits on EOI manually. This works in conjunction with the DD2 test in psi.c Signed-off-by: Benjamin Herrenschmidt --- hw/lpc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/lpc.c b/hw/lpc.c index 6bba61e..b5fbc6c 100644 --- a/hw/lpc.c +++ b/hw/lpc.c @@ -94,6 +94,7 @@ DEFINE_LOG_ENTRY(OPAL_RC_LPC_SYNC_PERF, OPAL_PLATFORM_ERR_EVT, OPAL_LPC, #define LPC_HC_IRQSER_START_4CLK 0x00000000 #define LPC_HC_IRQSER_START_6CLK 0x01000000 #define LPC_HC_IRQSER_START_8CLK 0x02000000 +#define LPC_HC_IRQSER_AUTO_CLEAR 0x00800000 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ #define LPC_HC_IRQSTAT 0x38 #define LPC_HC_IRQ_SERIRQ0 0x80000000u /* all bits down to ... */ @@ -621,7 +622,14 @@ static void lpc_setup_serirq(struct lpcm *lpc) /* Check whether we should enable serirq */ if (mask & LPC_HC_IRQ_SERIRQ_ALL) { rc = opb_write(lpc, lpc_reg_opb_base + LPC_HC_IRQSER_CTRL, - LPC_HC_IRQSER_EN | LPC_HC_IRQSER_START_4CLK, 4); + LPC_HC_IRQSER_EN | + LPC_HC_IRQSER_START_4CLK | + /* + * New mode bit for P9N DD2.0 (ignored otherwise) + * when set we no longer have to manually clear + * the SerIRQs on EOI. + */ + LPC_HC_IRQSER_AUTO_CLEAR, 4); DBG_IRQ("LPC: SerIRQ enabled\n"); } else { rc = opb_write(lpc, lpc_reg_opb_base + LPC_HC_IRQSER_CTRL,