From patchwork Fri May 26 08:28:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 767323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wYzqC0XVvz9s7y for ; Fri, 26 May 2017 18:30:47 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wYzqB6rYhzDqTX for ; Fri, 26 May 2017 18:30:46 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wYzpk5mvQzDqTQ for ; Fri, 26 May 2017 18:30:22 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4Q8ScqE003455 for ; Fri, 26 May 2017 04:30:13 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0b-001b2d01.pphosted.com with ESMTP id 2apb30m7mp-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 26 May 2017 04:30:13 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 26 May 2017 18:30:08 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4Q8Tx3a66322574 for ; Fri, 26 May 2017 18:30:07 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4Q8TYSE020094 for ; Fri, 26 May 2017 18:29:34 +1000 Received: from drishya.in.ibm.com (drishya.in.ibm.com [9.124.35.218]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4Q8TVo8019148; Fri, 26 May 2017 18:29:34 +1000 From: Vaidyanathan Srinivasan To: Stewart Smith Date: Fri, 26 May 2017 13:58:58 +0530 X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170526082900.11772-1-svaidy@linux.vnet.ibm.com> References: <20170526082900.11772-1-svaidy@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052608-0048-0000-0000-00000233EC05 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052608-0049-0000-0000-000047E2B68D Message-Id: <20170526082900.11772-3-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-26_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705260155 Subject: [Skiboot] [PATCH v8 2/4] occ: Fix Pstate ordering for P9 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Shilpasri G Bhat In P9 the pstate values are positive. They are continuous set of unsigned integers [0 to +N] where Pmax is 0 and Pmin is N. The linear ordering of pstates for P9 has changed compared to P8. P8 has neagtive pstate values advertised as [0 to -N] where Pmax is 0 and Pmin is -N. This patch adds helper routines to abstract pstate comparison with pmax and adds sanity pstate limit checks. This patch also fixes pstate arithmetic by using labs(). Suggested-by: Gautham R. Shenoy Signed-off-by: Shilpasri G Bhat --- hw/occ.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 4 deletions(-) diff --git a/hw/occ.c b/hw/occ.c index 2720b7b..039b0fc 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -84,6 +84,50 @@ DEFINE_LOG_ENTRY(OPAL_RC_OCC_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_OCC, OPAL_CEC_HARDWARE, OPAL_UNRECOVERABLE_ERR_GENERAL, OPAL_NA); +/* + * POWER9 and newer platforms have pstate values which are unsigned + * positive values. They are continuous set of unsigned integers + * [0 to +N] where Pmax is 0 and Pmin is N. The linear ordering of + * pstates for P9 has changed compared to P8. Where P8 has negative + * pstate values advertised as [0 to -N] where Pmax is 0 and + * Pmin is -N. The following routine helps to abstract pstate + * comparison with pmax and perform sanity checks on pstate limits. + */ + +/** + * cmp_pstates: Compares the given two pstates and determines which + * among them is associated with a higher pstate. + * + * @a,@b: The pstate ids of the pstates being compared. + * + * Returns: -1 : If pstate associated with @a is smaller than + * the pstate associated with @b. + * 0 : If pstates associated with @a and @b are equal. + * 1 : If pstate associated with @a is greater than + * the pstate associated with @b. + */ +static int (*cmp_pstates)(int a, int b); + +static int cmp_positive_pstates(int a, int b) +{ + if (a > b) + return -1; + else if (a < b) + return 1; + + return 0; +} + +static int cmp_negative_pstates(int a, int b) +{ + if (a < b) + return -1; + else if (a > b) + return 1; + + return 0; +} + /* Check each chip's HOMER/Sapphire area for PState valid bit */ static bool wait_for_all_occ_init(void) { @@ -214,15 +258,38 @@ static bool add_cpu_pstate_properties(s8 *pstate_nom) return false; } + /* + * Workload-Optimized-Frequency(WOF) or Ultra-Turbo is supported + * from version 2 onwards. If WOF is disabled then, the max + * ultra_turbo pstate will be equal to max turbo pstate. + */ if (occ_data->version > 1 && - occ_data->pstate_ultra_turbo > occ_data->pstate_turbo) + cmp_pstates(occ_data->pstate_ultra_turbo, + occ_data->pstate_turbo) > 0) ultra_turbo_en = true; else ultra_turbo_en = false; pmax = ultra_turbo_en ? occ_data->pstate_ultra_turbo : occ_data->pstate_turbo; - nr_pstates = pmax - occ_data->pstate_min + 1; + + /* Sanity check for pstate limits */ + if (cmp_pstates(occ_data->pstate_min, pmax) > 0) { + /** + * @fwts-label OCCInvalidPStateLimits + * @fwts-advice The min pstate is greater than the + * max pstate, this could be due to corrupted/invalid + * data in OCC-OPAL shared memory region. So OPAL has + * not added pstates to device tree. This means that + * CPU Frequency management will not be functional in + * the host. + */ + prlog(PR_ERR, "OCC: Invalid Pstate Limits. Pmin(%d) > Pmax (%d)\n", + occ_data->pstate_min, pmax); + return false; + } + + nr_pstates = labs(pmax - occ_data->pstate_min) + 1; prlog(PR_DEBUG, "OCC: Min %d Nom %d Max %d Nr States %d\n", occ_data->pstate_min, occ_data->pstate_nom, pmax, nr_pstates); @@ -319,15 +386,31 @@ static bool add_cpu_pstate_properties(s8 *pstate_nom) dt_core_max[i] = occ_data->core_max[i]; } + /* + * OCC provides pstate table entries in continuous descending order. + * Parse the pstate table to skip pstate_ids that are greater + * than Pmax. If a pstate_id is equal to Pmin then add it to + * the list and break from the loop as this is the last valid + * element in the pstate table. + */ for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) { - if (occ_data->pstates[i].id > pmax || - occ_data->pstates[i].id < occ_data->pstate_min) + if (cmp_pstates(occ_data->pstates[i].id, pmax) > 0) continue; + dt_id[j] = occ_data->pstates[i].id; dt_freq[j] = occ_data->pstates[i].freq_khz / 1000; dt_vdd[j] = occ_data->pstates[i].vdd; dt_vcs[j] = occ_data->pstates[i].vcs; j++; + + if (occ_data->pstates[i].id == occ_data->pstate_min) + break; + } + + if (j != nr_pstates) { + prerror("OCC: Expected pstates(%d) is not equal to parsed pstates(%d)\n", + nr_pstates, j); + goto out_free_vcs; } /* Add the device-tree entries */ @@ -533,6 +616,17 @@ void occ_pstates_init(void) if (occ_pstates_initialized) return; + switch (proc_gen) { + case proc_gen_p8: + cmp_pstates = cmp_negative_pstates; + break; + case proc_gen_p9: + cmp_pstates = cmp_positive_pstates; + break; + default: + return; + } + chip = next_chip(NULL); if (!chip->homer_base) { log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),