| Message ID | 20170504054704.31757-1-oohall@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
On Thu, 2017-05-04 at 15:47 +1000, Oliver O'Halloran wrote: > When saving the CTR and LR registers the skiboot exception handlers use the > 'stw' instruction which only saves the lower 32 bits of the register. Given > these are both 64 bit registers this leads to some strange register dumps, > for example: > > *********************************************** > Unexpected exception 200 ! > SRR0 : 0000000030016968 SRR1 : 9000000000201000 > HSRR0: 0000000000000180 HSRR1: 9000000000001000 > LR : 3003438830823f50 CTR : 3003438800000018 > CFAR : 00000000300168fc > CR : 40004208 XER: 00000000 > > In this dump the upper 32 bits of LR and CTR are actually stack gunk > which obscures the underlying issue. > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> > --- > asm/head.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/asm/head.S b/asm/head.S > index 8dabffd184a1..b10fbb554657 100644 > --- a/asm/head.S > +++ b/asm/head.S > @@ -198,8 +198,8 @@ _exception: > mflr %r6 > stw %r3,STACK_CR(%r1) > stw %r4,STACK_XER(%r1) > - stw %r5,STACK_CTR(%r1) > - stw %r5,STACK_LR(%r1) > + std %r5,STACK_CTR(%r1) > + std %r5,STACK_LR(%r1) > mfspr %r3,SPR_SRR0 > mfspr %r4,SPR_SRR1 > mfspr %r5,SPR_HSRR0
On Fri, 2017-05-05 at 16:03 +1000, Michael Neuling wrote: > > @@ -198,8 +198,8 @@ _exception: > > mflr %r6 > > stw %r3,STACK_CR(%r1) > > stw %r4,STACK_XER(%r1) > > - stw %r5,STACK_CTR(%r1) > > - stw %r5,STACK_LR(%r1) > > + std %r5,STACK_CTR(%r1) > > + std %r5,STACK_LR(%r1) You meant %r6 ? > > mfspr %r3,SPR_SRR0 > > mfspr %r4,SPR_SRR1 > > mfspr %r5,SPR_HSRR0
Oliver O'Halloran <oohall@gmail.com> writes: > When saving the CTR and LR registers the skiboot exception handlers use the > 'stw' instruction which only saves the lower 32 bits of the register. Given > these are both 64 bit registers this leads to some strange register dumps, > for example: > > *********************************************** > Unexpected exception 200 ! > SRR0 : 0000000030016968 SRR1 : 9000000000201000 > HSRR0: 0000000000000180 HSRR1: 9000000000001000 > LR : 3003438830823f50 CTR : 3003438800000018 > CFAR : 00000000300168fc > CR : 40004208 XER: 00000000 > > In this dump the upper 32 bits of LR and CTR are actually stack gunk > which obscures the underlying issue. > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Merged as of 70bc370883330c8b1076555c126647a3cdf88706 and the r5/r6 fixup spotted by Ben merged as of d55194c5d9ada77eee2c9a69814708304f34d334 and cherry-picked back into 5.4.x as of: e4055143dd6376bed4c94db6d95b73559a0bf702 4868b9816c7990fb0f26a0032fecfd5d9c9327b4
diff --git a/asm/head.S b/asm/head.S index 8dabffd184a1..b10fbb554657 100644 --- a/asm/head.S +++ b/asm/head.S @@ -198,8 +198,8 @@ _exception: mflr %r6 stw %r3,STACK_CR(%r1) stw %r4,STACK_XER(%r1) - stw %r5,STACK_CTR(%r1) - stw %r5,STACK_LR(%r1) + std %r5,STACK_CTR(%r1) + std %r5,STACK_LR(%r1) mfspr %r3,SPR_SRR0 mfspr %r4,SPR_SRR1 mfspr %r5,SPR_HSRR0
When saving the CTR and LR registers the skiboot exception handlers use the 'stw' instruction which only saves the lower 32 bits of the register. Given these are both 64 bit registers this leads to some strange register dumps, for example: *********************************************** Unexpected exception 200 ! SRR0 : 0000000030016968 SRR1 : 9000000000201000 HSRR0: 0000000000000180 HSRR1: 9000000000001000 LR : 3003438830823f50 CTR : 3003438800000018 CFAR : 00000000300168fc CR : 40004208 XER: 00000000 In this dump the upper 32 bits of LR and CTR are actually stack gunk which obscures the underlying issue. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> --- asm/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)