From patchwork Mon Jan 16 04:36:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 715572 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3v20ns4WcFz9t0J for ; Mon, 16 Jan 2017 15:37:21 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3v20ns3fMKzDqVQ for ; Mon, 16 Jan 2017 15:37:21 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3v20nT6NgzzDqSm for ; Mon, 16 Jan 2017 15:37:01 +1100 (AEDT) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v0G4ajux031771; Sun, 15 Jan 2017 22:36:48 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 15 Jan 2017 22:36:27 -0600 Message-Id: <20170116043635.25849-5-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170116043635.25849-1-benh@kernel.crashing.org> References: <20170116043635.25849-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 05/13] xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTL X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This bits saves the day if the special EX BARs happens to be misconfigured. There is no drawback to having it always set so let's do so. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 +- include/xive.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 81ff30c..6908835 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1594,7 +1594,7 @@ static bool xive_config_init(struct xive *x) uint64_t val __unused; /* Configure PC and VC page sizes and disable Linux trigger mode */ - xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K); + xive_regwx(x, CQ_PBI_CTL, CQ_PBI_PC_64K | CQ_PBI_VC_64K | CQ_PBI_FORCE_TM_LOCAL); if (x->last_reg_error) return false; diff --git a/include/xive.h b/include/xive.h index ab5ab80..e9a01c3 100644 --- a/include/xive.h +++ b/include/xive.h @@ -64,6 +64,7 @@ #define CQ_PBI_PC_64K PPC_BIT(5) #define CQ_PBI_VC_64K PPC_BIT(6) #define CQ_PBI_LNX_TRIG PPC_BIT(7) +#define CQ_PBI_FORCE_TM_LOCAL PPC_BIT(22) #define CQ_PBO_CTL 0x108 #define CQ_AIB_CTL 0x110 #define X_CQ_RST_CTL 0x23 @@ -296,6 +297,10 @@ * * Then we have all these "special" CI ops at these offset that trigger * all sorts of side effects: + * + * We can OR'in these a cache line index from 0...3 (ie, 0, 0x80, 0x100, 0x180) + * to select a specific snooper. 0 is pretty busy so 0x80 or 0x100 is recommended + * XXX TODO. add that and find way to tell KVM about it. */ #define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/ #define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */