From patchwork Wed Aug 1 20:01:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 952371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41gknd2Q42z9s3Z for ; Thu, 2 Aug 2018 06:05:41 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41gknd16p3zF1s5 for ; Thu, 2 Aug 2018 06:05:41 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41gkhp15Q5zF1Rs for ; Thu, 2 Aug 2018 06:01:29 +1000 (AEST) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w71JxvO3129754 for ; Wed, 1 Aug 2018 16:01:26 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0b-001b2d01.pphosted.com with ESMTP id 2kkjahtp74-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 01 Aug 2018 16:01:25 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 1 Aug 2018 14:01:22 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w71K1LwV10813820 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 1 Aug 2018 13:01:21 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A39117806A; Wed, 1 Aug 2018 14:01:21 -0600 (MDT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 88D3878060; Wed, 1 Aug 2018 14:01:21 -0600 (MDT) Received: from arbab-laptop.localdomain (unknown [9.24.3.46]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 1 Aug 2018 14:01:21 -0600 (MDT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id DD97F460584; Wed, 1 Aug 2018 15:01:19 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 1 Aug 2018 15:01:17 -0500 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1533153679-10109-1-git-send-email-arbab@linux.ibm.com> References: <1533153679-10109-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18080120-0016-0000-0000-000009111044 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009468; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01068926; UDB=6.00549578; IPR=6.00847266; MB=3.00022445; MTD=3.00000008; XFM=3.00000015; UTC=2018-08-01 20:01:24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18080120-0017-0000-0000-00003FD76254 Message-Id: <1533153679-10109-5-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-08-01_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=721 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1808010202 Subject: [Skiboot] [PATCH 4/6] npu2: Don't open code NPU2_RELAXED_ORDERING_CFG2 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Make the code that initializes these registers more descriptive by using macros instead of open coded literals. No functional change. Signed-off-by: Reza Arbab Reviewed-By: Alistair Popple --- hw/npu2.c | 31 +++++++++++++------------------ include/npu2-regs.h | 2 ++ 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/npu2.c b/hw/npu2.c index acd56c1..9748536 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -857,7 +857,8 @@ static void npu2_mcd_init(struct npu2 *p) static void npu2_hw_init(struct npu2 *p) { - uint64_t val; + uint64_t reg, val; + int s, b; npu2_ioda_reset(&p->phb_nvlink, false); @@ -916,6 +917,17 @@ static void npu2_hw_init(struct npu2 *p) NPU2DBG(p, "Using large memory map + MCD disabled\n"); p->gpu_map_type = GPU_MEM_4T_DOWN; } + + /* Static initialization of every relaxed-ordering cfg[2] register */ + val = NPU2_RELAXED_ORDERING_CMD_CL_RD_NC_F0 | + NPU2_RELAXED_ORDERING_SOURCE4_RDENA; + + for (s = NPU2_STACK_STCK_0; s <= NPU2_STACK_STCK_2; s++) { + for (b = NPU2_BLOCK_SM_0; b <= NPU2_BLOCK_SM_3; b++) { + reg = NPU2_REG_OFFSET(s, b, NPU2_RELAXED_ORDERING_CFG2); + npu2_write(p, reg, val); + } + } } static int64_t npu2_map_pe_dma_window_real(struct phb *phb, @@ -1416,23 +1428,6 @@ static void npu2_probe_phb(struct dt_node *dn) xscom_write_mask(gcid, 0x5011510, val, val); xscom_write_mask(gcid, 0x5011530, val, val); - /* - * Enable relaxed ordering for peer-to-peer reads - */ - val = PPC_BIT(5) | PPC_BIT(29); - xscom_write_mask(gcid, 0x501100c, val, val); - xscom_write_mask(gcid, 0x501103c, val, val); - xscom_write_mask(gcid, 0x501106c, val, val); - xscom_write_mask(gcid, 0x501109c, val, val); - xscom_write_mask(gcid, 0x501120c, val, val); - xscom_write_mask(gcid, 0x501123c, val, val); - xscom_write_mask(gcid, 0x501126c, val, val); - xscom_write_mask(gcid, 0x501129c, val, val); - xscom_write_mask(gcid, 0x501140c, val, val); - xscom_write_mask(gcid, 0x501143c, val, val); - xscom_write_mask(gcid, 0x501146c, val, val); - xscom_write_mask(gcid, 0x501149c, val, val); - val = PPC_BIT(6) | PPC_BIT(7) | PPC_BIT(11); xscom_write_mask(gcid, 0x5011009, val, PPC_BITMASK(6,11)); xscom_write_mask(gcid, 0x5011039, val, PPC_BITMASK(6,11)); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 4a17ac8..d9db988 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -155,6 +155,8 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define NPU2_RELAXED_ORDERING_CFG0 0x050 #define NPU2_RELAXED_ORDERING_CFG1 0x058 #define NPU2_RELAXED_ORDERING_CFG2 0x060 +#define NPU2_RELAXED_ORDERING_CMD_CL_RD_NC_F0 PPC_BIT(5) +#define NPU2_RELAXED_ORDERING_SOURCE4_RDENA PPC_BIT(29) #define NPU2_NTL0_BAR 0x068 #define NPU2_NTL1_BAR 0x070 #define NPU2_NTL_BAR_ENABLE PPC_BIT(0)