From patchwork Mon Apr 16 17:34:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mahesh J Salgaonkar X-Patchwork-Id: 898842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40PwYX1mJwz9s3G for ; Tue, 17 Apr 2018 03:37:04 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40PwYX09v9zF1xm for ; Tue, 17 Apr 2018 03:37:04 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=mahesh@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40PwVl0B6JzF1wJ for ; Tue, 17 Apr 2018 03:34:38 +1000 (AEST) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w3GHXHj9031689 for ; Mon, 16 Apr 2018 13:34:36 -0400 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 2hcwd4h88w-1 (version=TLSv1.2 cipher=AES256-SHA256 bits=256 verify=NOT) for ; Mon, 16 Apr 2018 13:34:35 -0400 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 16 Apr 2018 18:34:31 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w3GHYVrs57540682; Mon, 16 Apr 2018 17:34:31 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 80FB352049; Mon, 16 Apr 2018 17:25:21 +0100 (BST) Received: from jupiter.in.ibm.com (unknown [9.102.1.147]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 046BA5203F; Mon, 16 Apr 2018 17:25:20 +0100 (BST) From: Mahesh J Salgaonkar To: skiboot list Date: Mon, 16 Apr 2018 23:04:29 +0530 In-Reply-To: <152389987405.2566.355149283827806637.stgit@jupiter.in.ibm.com> References: <152389987405.2566.355149283827806637.stgit@jupiter.in.ibm.com> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18041617-0040-0000-0000-0000044E2F00 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18041617-0041-0000-0000-000020F271F6 Message-Id: <152390006973.2566.12036488100857139008.stgit@jupiter.in.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-16_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1804160155 Subject: [Skiboot] [PATCH v2 14/15] opal/hmi: Generate hmi event for recovered HDEC parity error. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Mahesh Salgaonkar Signed-off-by: Mahesh Salgaonkar --- core/hmi.c | 5 ++--- hw/chiptod.c | 11 +++++++---- include/chiptod.h | 2 +- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 9b98fbd98..53cb84712 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -1019,10 +1019,9 @@ static int handle_all_core_tfac_error(uint64_t tfmr, uint64_t *out_flags) hmi_rendez_vous(2); /* We can now clear the error conditions in the core. */ - if (!tfmr_clear_core_errors(tfmr)) { - recover = 0; + recover = tfmr_clear_core_errors(tfmr); + if (recover == 0) goto error_out; - } /* Third rendez-vous. We could in theory do the timebase resync as * part of the previous one, but I prefer having all the error diff --git a/hw/chiptod.c b/hw/chiptod.c index 28ed8973a..df1274ca8 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -1491,18 +1491,21 @@ void tfmr_cleanup_core_errors(uint64_t tfmr) } } -bool tfmr_clear_core_errors(uint64_t tfmr) +int tfmr_clear_core_errors(uint64_t tfmr) { uint64_t tfmr_reset_errors = 0; - if (tfmr & SPR_TFMR_HDEC_PARITY_ERROR) - tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR; + /* return -1 if there is nothing to be fixed. */ + if (!(tfmr & SPR_TFMR_HDEC_PARITY_ERROR)) + return -1; + + tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR; /* Write TFMR twice to clear the error */ mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors); mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors); - return true; + return 1; } /* diff --git a/include/chiptod.h b/include/chiptod.h index 5860e34d2..3717e6674 100644 --- a/include/chiptod.h +++ b/include/chiptod.h @@ -33,7 +33,7 @@ extern int chiptod_recover_tb_errors(bool *out_resynced); extern bool tfmr_recover_local_errors(uint64_t tfmr); extern bool recover_corrupt_tfmr(void); extern void tfmr_cleanup_core_errors(uint64_t tfmr); -extern bool tfmr_clear_core_errors(uint64_t tfmr); +extern int tfmr_clear_core_errors(uint64_t tfmr); extern void chiptod_reset_tb(void); extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable); extern bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr,