From patchwork Wed Sep 6 22:35:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 810822 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xndhG6PL3z9s82 for ; Thu, 7 Sep 2017 08:35:26 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xndhG5fBlzDrWH for ; Thu, 7 Sep 2017 08:35:26 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xndh65KGBzDrVj for ; Thu, 7 Sep 2017 08:35:17 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v86MNuVe090721 for ; Wed, 6 Sep 2017 18:35:15 -0400 Received: from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ctq9s2ykg-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 06 Sep 2017 18:35:14 -0400 Received: from localhost by e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 6 Sep 2017 18:35:11 -0400 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v86MZAKl31981602; Wed, 6 Sep 2017 22:35:10 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A600AC04A; Wed, 6 Sep 2017 18:35:38 -0400 (EDT) Received: from arbab-laptop.localdomain (unknown [9.53.92.213]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id E4566AC03A; Wed, 6 Sep 2017 18:35:37 -0400 (EDT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 3E68D46074E; Wed, 6 Sep 2017 17:35:09 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 6 Sep 2017 17:35:09 -0500 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 17090622-0044-0000-0000-0000038A1D86 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007679; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000226; SDB=6.00913269; UDB=6.00458350; IPR=6.00693531; BA=6.00005574; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017041; XFM=3.00000015; UTC=2017-09-06 22:35:12 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17090622-0045-0000-0000-000007B91D7C Message-Id: <1504737309-26981-1-git-send-email-arbab@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-06_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709060319 Subject: [Skiboot] [PATCH] npu2: hw-procedures: Enable low power mode X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple , Andrew Donnellan MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a procedure which sets the NTL low power config register. Signed-off-by: Reza Arbab --- hw/npu2-hw-procedures.c | 18 +++++++++++++++++- include/npu2-regs.h | 6 ++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index a140aed..24feb03 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -310,9 +310,25 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0); } + return PROCEDURE_NEXT; +} + +/* Procedure 1.2.11 - Enable Low Power Mode */ +static uint32_t enable_low_power(struct npu2_dev *ndev) +{ + uint64_t val; + + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 1); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 8); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 15); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 8); + npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val); + return PROCEDURE_COMPLETE; } -DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete); +DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete, + enable_low_power); /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */ static uint32_t phy_tx_zcal(struct npu2_dev *ndev) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 86e2658..24d8549 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_MISC_CFG1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0C0) #define NPU2_NTL_SCRATCH1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0D0) #define NPU2_NTL_LOW_POWER_CFG(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0E0) +#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE PPC_BIT(0) +#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE PPC_BIT(1) +#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG PPC_BITMASK(2,7) +#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH PPC_BITMASK(8,19) +#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH PPC_BITMASK(20,31) +#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH PPC_BITMASK(32,43) #define NPU2_NTL_DBG_INHIBIT_CFG(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x220) #define NPU2_NTL_DISPLAY_CTL(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x280) #define NPU2_NTL_DISPLAY_DATA0(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x288)