From patchwork Tue Jul 18 22:01:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shilpasri G Bhat X-Patchwork-Id: 790658 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xBvYd3dQTz9s7g for ; Wed, 19 Jul 2017 08:13:09 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xBvYd2ZP4zDrJx for ; Wed, 19 Jul 2017 08:13:09 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xBvKG63qRzDrD8 for ; Wed, 19 Jul 2017 08:02:26 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6ILupJv132299 for ; Tue, 18 Jul 2017 18:02:25 -0400 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0a-001b2d01.pphosted.com with ESMTP id 2bspj732q4-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 18 Jul 2017 18:02:25 -0400 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 19 Jul 2017 08:02:20 +1000 Received: from d23av06.au.ibm.com (d23av06.au.ibm.com [9.190.235.151]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v6IM2KTg27197590 for ; Wed, 19 Jul 2017 08:02:20 +1000 Received: from d23av06.au.ibm.com (localhost [127.0.0.1]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v6IM2Jen030908 for ; Wed, 19 Jul 2017 08:02:20 +1000 Received: from oc4502181600.ibm.com ([9.79.213.106]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v6IM20VX030206; Wed, 19 Jul 2017 08:02:17 +1000 From: Shilpasri G Bhat To: stewart@linux.vnet.ibm.com, cyrilbur@gmail.com Date: Wed, 19 Jul 2017 03:31:32 +0530 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1500415292-23257-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> References: <1500415292-23257-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17071822-0008-0000-0000-0000015150BA X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17071822-0009-0000-0000-000009822625 Message-Id: <1500415292-23257-4-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-18_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1706020000 definitions=main-1707180340 Subject: [Skiboot] [PATCH V6 3/3] occ: Add support to change power-shifting-ratio X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, ego@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Signed-off-by: Shilpasri G Bhat --- hw/occ.c | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/opal-api.h | 4 +- 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/hw/occ.c b/hw/occ.c index 24ead8e..74094b6 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -1194,6 +1194,7 @@ exit: } static void occ_add_powercap_sensors(void); +static void occ_add_psr_sensors(void); static void occ_cmd_interface_init(void) { @@ -1229,6 +1230,7 @@ static void occ_cmd_interface_init(void) i++; } occ_add_powercap_sensors(); + occ_add_psr_sensors(); } /* Powercap interface */ @@ -1340,6 +1342,112 @@ int occ_set_powercap(int token, u32 pcap) return opal_occ_command(&chips[i], token, &pcap_data); }; +/* Power-Shifting Ratio */ +enum psr_type { + PSR_TYPE_CPU_TO_GPU, /* 0% Cap GPU first, 100% Cap CPU first */ +}; + +static int opal_get_power_shifting_ratio(u32 handle, int token __unused, + int *ratio) +{ + struct occ_pstate_table *pdata; + struct occ_dynamic_data *ddata; + struct proc_chip *chip; + int type = (handle >> 24) & 0xF; + int i = handle & 0xF; + + if (type != PSR_TYPE_CPU_TO_GPU) + return OPAL_UNSUPPORTED; + + if (i > nr_occs || i < 0) + return OPAL_PARAMETER; + + chip = get_chip(chips[i].chip_id); + pdata = get_occ_pstate_table(chip); + if (!pdata->valid) + return OPAL_BUSY; + + ddata = get_occ_dynamic_data(chip); + *ratio = ddata->pwr_shifting_ratio; + return OPAL_SUCCESS; +} + +static u8 psr_cdata; +static struct opal_occ_cmd_data psr_data = { + .data = &psr_cdata, + .cmd = OCC_CMD_SET_POWER_SHIFTING_RATIO, +}; + +static int opal_set_power_shifting_ratio(u32 handle, int token, int ratio) +{ + struct occ_pstate_table *pdata; + struct occ_dynamic_data *ddata; + struct proc_chip *chip; + int type = (handle >> 24) & 0xF; + int i = handle & 0xF; + + if (type != PSR_TYPE_CPU_TO_GPU) + return OPAL_UNSUPPORTED; + + if (ratio < 0 || ratio > 100) + return OPAL_PARAMETER; + + if (i > nr_occs || i < 0) + return OPAL_PARAMETER; + + chip = next_chip(NULL); + pdata = get_occ_pstate_table(chip); + if (!pdata->valid) + return OPAL_BUSY; + + if (!(PPC_BIT16(*chips[i].occ_state) & + occ_cmds[psr_data.cmd].state_mask)) + return OPAL_WRONG_STATE; + + ddata = get_occ_dynamic_data(chip); + if (ratio == ddata->pwr_shifting_ratio) + return OPAL_SUCCESS; + + psr_cdata = ratio; + return opal_occ_command(&chips[i], token, &psr_data); +} + +static void occ_add_psr_sensors(void) +{ + struct dt_node *node, *cnode, *power_mgt; + int i; + + power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt"); + if (!power_mgt) { + prerror("OCC: dt node /ibm,opal/power-mgt not found\n"); + return; + } + + node = dt_new(power_mgt, "psr"); + if (!node) { + prerror("OCC: Failed to create power-shifting-ratio node\n"); + return; + } + + for (i = 0; i < nr_occs; i++) { + char name[20]; + u32 handle = (PSR_TYPE_CPU_TO_GPU << 24) | i; + + cnode = dt_new_addr(node, "cpu-to-gpu", handle); + if (!cnode) { + prerror("OCC: Failed to create power-shifting-ratio node\n"); + return; + } + + snprintf(name, 20, "cpu_to_gpu_%d", chips[i].chip_id); + dt_add_property_string(cnode, "label", name); + dt_add_property_cells(cnode, "handle", handle); + } + + opal_register(OPAL_GET_PSR, opal_get_power_shifting_ratio, 3); + opal_register(OPAL_SET_PSR, opal_set_power_shifting_ratio, 3); +} + /* CPU-OCC PState init */ /* Called after OCC init on P8 and P9 */ void occ_pstates_init(void) diff --git a/include/opal-api.h b/include/opal-api.h index 3ad4898..2717a0d 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -210,7 +210,9 @@ #define OPAL_IMC_COUNTERS_STOP 151 #define OPAL_GET_POWERCAP 152 #define OPAL_SET_POWERCAP 153 -#define OPAL_LAST 153 +#define OPAL_GET_PSR 154 +#define OPAL_SET_PSR 155 +#define OPAL_LAST 155 /* Device tree flags */