From patchwork Thu May 4 08:34:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 758417 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wJT0b6dTfz9rxj for ; Thu, 4 May 2017 18:37:03 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wJT0b5hjSzDqKJ for ; Thu, 4 May 2017 18:37:03 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wJSzy1FrQzDqFV for ; Thu, 4 May 2017 18:36:29 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v448Xjaf002146 for ; Thu, 4 May 2017 04:36:19 -0400 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0b-001b2d01.pphosted.com with ESMTP id 2a7m0r5eb8-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 May 2017 04:36:19 -0400 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 May 2017 18:36:13 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v448a47Z6160826 for ; Thu, 4 May 2017 18:36:12 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v448Zenu022676 for ; Thu, 4 May 2017 18:35:40 +1000 Received: from aksadiga.in.ibm.com (aksadiga.in.ibm.com [9.124.35.243]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v448ZXrk021602; Thu, 4 May 2017 18:35:39 +1000 From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 May 2017 14:04:44 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1493886884-7659-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1493886884-7659-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17050408-0008-0000-0000-0000012857A1 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17050408-0009-0000-0000-000009568CA7 Message-Id: <1493886884-7659-5-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-04_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705040143 Subject: [Skiboot] [RFC v1 4/4] SLW: Enable Stop4 as the deepest idle state X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Adding stop4 to device tree as the deepest idle state for power9 dd1. The latency is configured such that they are not chosen for cpuidle and will only be used for cpuhotplug. Use a common variable has_wakeup_engine instead of has_slw to tell if the a) SLW image is populated in case of power8 b) CME image is populated in case of power9 Currently we expect CME to be loaded if homer address is known ( except for simulators) Signed-off-by: Akshay Adiga --- Changes in v1 : Changes in commit message hw/slw.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index aeb8388..93d5aae 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -700,6 +700,22 @@ static struct cpu_idle_states power9_dd1_cpu_idle_states[] = { | OPAL_PM_PSSCR_TR(3) \ | OPAL_PM_PSSCR_ESL \ | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop4", + .latency_ns = 2060000, + .residency_ns = 1000000, + .flags = 1*OPAL_PM_DEC_STOP \ + | 1*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 1*OPAL_PM_LOSE_HYP_CONTEXT \ + | 1*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_DEEP, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(4) \ + | OPAL_PM_PSSCR_MTL(7) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK } }; @@ -712,7 +728,7 @@ void add_cpu_idle_state_properties(void) int nr_states; bool can_sleep = true; - bool has_slw = true; + bool has_wakeup_engine = true; /* p8=SLW; p9=CME */ bool has_stop_inst = false; u8 i; @@ -802,8 +818,11 @@ void add_cpu_idle_state_properties(void) } /* Enable deep idle states only if slw image is intact */ - has_slw = (chip->slw_base && chip->slw_bar_size && - chip->slw_image_size); + if (proc_gen == proc_gen_p8) + has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && + chip->slw_image_size); + else /*if (proc_gen == proc_gen_p9)*/ + has_wakeup_engine = !(QUIRK_MAMBO_CALLOUTS); /* * Currently we can't append strings and cells to dt properties. @@ -831,7 +850,7 @@ void add_cpu_idle_state_properties(void) if (has_stop_inst) { /* Power 9 / POWER ISA 3.0 */ supported_states_mask = OPAL_PM_STOP_INST_FAST; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; } else { /* Power 7 and Power 8 */ @@ -839,7 +858,7 @@ void add_cpu_idle_state_properties(void) if (can_sleep) supported_states_mask |= OPAL_PM_SLEEP_ENABLED | OPAL_PM_SLEEP_ENABLED_ER1; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) {