From patchwork Thu May 4 08:34:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 758415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wJT0G3qQZz9rxj for ; Thu, 4 May 2017 18:36:46 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wJT0G34c2zDqJt for ; Thu, 4 May 2017 18:36:46 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wJSzr3RlFzDqFG for ; Thu, 4 May 2017 18:36:24 +1000 (AEST) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v448Xitl089455 for ; Thu, 4 May 2017 04:36:14 -0400 Received: from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147]) by mx0a-001b2d01.pphosted.com with ESMTP id 2a73gxrymx-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 04 May 2017 04:36:14 -0400 Received: from localhost by e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 May 2017 18:36:10 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v448a2sS49283108 for ; Thu, 4 May 2017 18:36:10 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v448ZbKH022582 for ; Thu, 4 May 2017 18:35:37 +1000 Received: from aksadiga.in.ibm.com (aksadiga.in.ibm.com [9.124.35.243]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v448ZXri021602; Thu, 4 May 2017 18:35:36 +1000 From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 4 May 2017 14:04:42 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1493886884-7659-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1493886884-7659-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17050408-0016-0000-0000-0000023754A9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17050408-0017-0000-0000-000006B30380 Message-Id: <1493886884-7659-3-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-04_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705040143 Subject: [Skiboot] [RFC v1 2/4] SLW: Add opal_slw_set_reg support for power9 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This OPAL call is made from Linux to OPAL to configure valuse in various SPRs after wakeup from a deep idle state. Signed-off-by: Akshay Adiga --- Changes in v1: Change in commit message. hw/slw.c | 52 ++++++++++++++++++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index 6503fa7..e4ab2c2 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -1324,33 +1324,49 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) assert(c); chip = get_chip(c->chip_id); assert(chip); - image = (void *) chip->slw_base; - /* Check of the SPR is supported by libpore */ - for ( i=0; i < SLW_SPR_REGS_SIZE ; i++) { - if (sprn == SLW_SPR_REGS[i].value) { - spr_is_supported = 1; - break; + + if (chip->type == PROC_CHIP_P9_NIMBUS || + chip->type == PROC_CHIP_P9_CUMULUS ) { + if(!chip->homer_base) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: HOMER base not set %x\n", + chip->id); + return OPAL_INTERNAL_ERROR; } - } - if (!spr_is_supported) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Trying to set unsupported spr for CPU %x\n", - c->pir); - return OPAL_UNSUPPORTED; - } + rc = p9_stop_save_cpureg((void *) chip->homer_base, + sprn, val, cpu_pir); + + } else { /* Assuming its P8 */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, sprn, - val, cpu_get_core_index(c), + /* Check of the SPR is supported by libpore */ + for ( i=0; i < SLW_SPR_REGS_SIZE ; i++) { + if (sprn == SLW_SPR_REGS[i].value) { + spr_is_supported = 1; + break; + } + } + if (!spr_is_supported) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Trying to set unsupported spr for CPU %x\n", + c->pir); + return OPAL_UNSUPPORTED; + } + image = (void *) chip->slw_base; + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + sprn, val, + cpu_get_core_index(c), cpu_get_thread_index(c)); + } if (rc) { log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set spr for CPU %x\n", - c->pir); + "SLW: Failed to set spr %llx for CPU %x\n", + sprn, c->pir); return OPAL_INTERNAL_ERROR; } - + prlog(PR_NOTICE, "SLW: restore spr:0x%llx on c:0x%x with 0x%llx\n", + sprn, c->pir, val); return OPAL_SUCCESS; }