From patchwork Sat Apr 1 06:13:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shilpasri G Bhat X-Patchwork-Id: 745891 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vw7P153vSz9s03 for ; Sat, 1 Apr 2017 17:14:13 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vw7P13PLszDqJC for ; Sat, 1 Apr 2017 17:14:13 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vw7Nt6ljMzDqC4 for ; Sat, 1 Apr 2017 17:14:06 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v316Dv01004675 for ; Sat, 1 Apr 2017 02:13:59 -0400 Received: from e28smtp09.in.ibm.com (e28smtp09.in.ibm.com [125.16.236.9]) by mx0a-001b2d01.pphosted.com with ESMTP id 29j53fjkwb-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sat, 01 Apr 2017 02:13:58 -0400 Received: from localhost by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Sat, 1 Apr 2017 11:43:47 +0530 Received: from d28av03.in.ibm.com (d28av03.in.ibm.com [9.184.220.65]) by d28relay01.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v316Dl1Y13828280 for ; Sat, 1 Apr 2017 11:43:47 +0530 Received: from d28av03.in.ibm.com (localhost [127.0.0.1]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v316DjHR014827 for ; Sat, 1 Apr 2017 11:43:46 +0530 Received: from oc4502181600.ibm.com ([9.124.210.79]) by d28av03.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v316DjfI014811; Sat, 1 Apr 2017 11:43:45 +0530 From: Shilpasri G Bhat To: mikey@neuling.org Date: Sat, 1 Apr 2017 11:43:39 +0530 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-MML: disable x-cbid: 17040106-0032-0000-0000-00000206C89A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17040106-0033-0000-0000-0000123B1F0E Message-Id: <1491027219-5349-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-01_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704010060 Subject: [Skiboot] [PATCH] occ: irq: Fix SCOM address for OCC_MISC register X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, svaidyan@in.ibm.com, skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch fixes the SCOM address for OCC_MISC register which is used for OCC interupts. Originally-from: Michael Neuling Signed-off-by: Shilpasri G Bhat --- hw/occ.c | 61 +++++++++++++++++++++++++++++++++++++++++++++---------- hw/psi.c | 4 ++-- include/skiboot.h | 7 +++++-- 3 files changed, 57 insertions(+), 15 deletions(-) diff --git a/hw/occ.c b/hw/occ.c index 7b502b4..2ffb677 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -1279,17 +1279,25 @@ static struct fsp_client fsp_occ_client = { .message = fsp_occ_msg, }; -#define OCB_OCI_OCCMISC 0x6a020 -#define OCB_OCI_OCCMISC_AND 0x6a021 -#define OCB_OCI_OCCMISC_OR 0x6a022 +#define P8_OCB_OCI_OCCMISC 0x6a020 +#define P8_OCB_OCI_OCCMISC_AND 0x6a021 +#define P8_OCB_OCI_OCCMISC_OR 0x6a022 + +#define P9_OCB_OCI_OCCMISC 0x6c080 +#define P9_OCB_OCI_OCCMISC_AND 0x6c081 /* Write Clear */ +#define P9_OCB_OCI_OCCMISC_OR 0x6c082 + #define OCB_OCI_OCIMISC_IRQ PPC_BIT(0) #define OCB_OCI_OCIMISC_IRQ_TMGT PPC_BIT(1) #define OCB_OCI_OCIMISC_IRQ_SLW_TMR PPC_BIT(14) #define OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY PPC_BIT(15) -#define OCB_OCI_OCIMISC_MASK (OCB_OCI_OCIMISC_IRQ_TMGT | \ + +#define P8_OCB_OCI_OCIMISC_MASK (OCB_OCI_OCIMISC_IRQ_TMGT | \ OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY | \ OCB_OCI_OCIMISC_IRQ_SLW_TMR) +#define P9_OCB_OCI_OCIMISC_MASK OCB_OCI_OCIMISC_IRQ_TMGT + void occ_send_dummy_interrupt(void) { struct psi *psi; @@ -1312,17 +1320,17 @@ void occ_send_dummy_interrupt(void) return; } - xscom_write(psi->chip_id, OCB_OCI_OCCMISC_OR, + xscom_write(psi->chip_id, P8_OCB_OCI_OCCMISC_OR, OCB_OCI_OCIMISC_IRQ | OCB_OCI_OCIMISC_IRQ_OPAL_DUMMY); } -void occ_interrupt(uint32_t chip_id) +void occ_p8_interrupt(uint32_t chip_id) { uint64_t ireg; int64_t rc; /* The OCC interrupt is used to mux up to 15 different sources */ - rc = xscom_read(chip_id, OCB_OCI_OCCMISC, &ireg); + rc = xscom_read(chip_id, P8_OCB_OCI_OCCMISC, &ireg); if (rc) { prerror("OCC: Failed to read interrupt status !\n"); /* Should we mask it in the XIVR ? */ @@ -1331,7 +1339,7 @@ void occ_interrupt(uint32_t chip_id) prlog(PR_TRACE, "OCC: IRQ received: %04llx\n", ireg >> 48); /* Clear the bits */ - xscom_write(chip_id, OCB_OCI_OCCMISC_AND, ~ireg); + xscom_write(chip_id, P8_OCB_OCI_OCCMISC_AND, ~ireg); /* Dispatch */ if (ireg & OCB_OCI_OCIMISC_IRQ_TMGT) @@ -1343,9 +1351,40 @@ void occ_interrupt(uint32_t chip_id) * OCCMISC_AND write. Check if there are any new source bits set, * and trigger another interrupt if so. */ - rc = xscom_read(chip_id, OCB_OCI_OCCMISC, &ireg); - if (!rc && (ireg & OCB_OCI_OCIMISC_MASK)) - xscom_write(chip_id, OCB_OCI_OCCMISC_OR, OCB_OCI_OCIMISC_IRQ); + rc = xscom_read(chip_id, P8_OCB_OCI_OCCMISC, &ireg); + if (!rc && (ireg & P8_OCB_OCI_OCIMISC_MASK)) + xscom_write(chip_id, P8_OCB_OCI_OCCMISC_OR, + OCB_OCI_OCIMISC_IRQ); +} + +void occ_p9_interrupt(uint32_t chip_id) +{ + u64 ireg; + s64 rc; + + /* The OCC interrupt is used to mux up to 15 different sources */ + rc = xscom_read(chip_id, P9_OCB_OCI_OCCMISC, &ireg); + if (rc) { + prerror("OCC: Failed to read interrupt status !\n"); + return; + } + prlog(PR_TRACE, "OCC: IRQ received: %04llx\n", ireg >> 48); + + /* Clear the bits */ + xscom_write(chip_id, P9_OCB_OCI_OCCMISC_AND, ireg); + + /* Dispatch */ + if (ireg & OCB_OCI_OCIMISC_IRQ_TMGT) + prd_tmgt_interrupt(chip_id); + + /* We may have masked-out OCB_OCI_OCIMISC_IRQ in the previous + * OCCMISC_AND write. Check if there are any new source bits set, + * and trigger another interrupt if so. + */ + rc = xscom_read(chip_id, P9_OCB_OCI_OCCMISC, &ireg); + if (!rc && (ireg & P9_OCB_OCI_OCIMISC_MASK)) + xscom_write(chip_id, P9_OCB_OCI_OCCMISC_OR, + OCB_OCI_OCIMISC_IRQ); } void occ_fsp_init(void) diff --git a/hw/psi.c b/hw/psi.c index 089f429..cc7db44 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -485,7 +485,7 @@ static void psihb_p8_interrupt(struct irq_source *is, uint32_t isn) psihb_interrupt(is, isn); break; case P8_IRQ_PSI_OCC: - occ_interrupt(psi->chip_id); + occ_p8_interrupt(psi->chip_id); break; case P8_IRQ_PSI_FSI: printf("PSI: FSI irq received\n"); @@ -572,7 +572,7 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) psihb_interrupt(is, isn); break; case P9_PSI_IRQ_OCC: - occ_interrupt(psi->chip_id); + occ_p9_interrupt(psi->chip_id); break; case P9_PSI_IRQ_FSI: printf("PSI: FSI irq received\n"); diff --git a/include/skiboot.h b/include/skiboot.h index 8bc767a..2b1f8a5 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -254,10 +254,13 @@ enum { extern void uart_set_console_policy(int policy); extern bool uart_enabled(void); -/* OCC interrupt */ -extern void occ_interrupt(uint32_t chip_id); +/* OCC interrupt for P8 */ +extern void occ_p8_interrupt(uint32_t chip_id); extern void occ_send_dummy_interrupt(void); +/* OCC interrupt for P9 */ +extern void occ_p9_interrupt(uint32_t chip_id); + /* OCC load support */ extern void occ_poke_load_queue(void);