From patchwork Thu Mar 9 00:38:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 736785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vds2m0VH4z9s1y for ; Thu, 9 Mar 2017 11:38:56 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vds2l6NqzzDqYP for ; Thu, 9 Mar 2017 11:38:55 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vds2c1hdwzDqXc for ; Thu, 9 Mar 2017 11:38:47 +1100 (AEDT) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v290ceNs025477 for ; Wed, 8 Mar 2017 18:38:41 -0600 Message-ID: <1489019919.2870.174.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 09 Mar 2017 11:38:39 +1100 X-Mailer: Evolution 3.22.5 (3.22.5-1.fc25) Mime-Version: 1.0 Subject: [Skiboot] [PATCH/RFC] affinity: Use fabric node ID on most systems X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Except Murano where we stick to the module ID from HDAT Signed-off-by: Benjamin Herrenschmidt --- core/affinity.c | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/core/affinity.c b/core/affinity.c index 9f489d3..d3df910 100644 --- a/core/affinity.c +++ b/core/affinity.c @@ -54,35 +54,37 @@ static uint32_t get_chip_node_id(struct proc_chip *chip) { - /* If the xscom node has an ibm,ccm-node-id property, use it */ - if (dt_has_node_property(chip->devnode, "ibm,ccm-node-id", NULL)) - return dt_prop_get_u32(chip->devnode, "ibm,ccm-node-id"); - /* * Else use the 3 top bits of the chip ID which should be - * the node on both P7 and P8 + * the node on P7, P8 and P9 */ return chip->id >> 3; } void add_associativity_ref_point(void) { - int ref2 = 0x4; + uint32_t ref2 = 0x1; /* * Note about our use of reference points: * - * Linux currently supports two levels of NUMA. We use the first + * Linux currently supports two levels of NUMA. It uses the first * reference point for the node ID and the second reference point - * for a second level of affinity. We always use the chip ID (4) - * for the first reference point. + * for a second level of affinity. + * + * We always pass the chip ID (4) for the first reference point. + * + * We pass the "module ID" (3) as the second point. When it doesn't + * exist in the DT we inherit the chip node ID which on Venice + * works fine. On FSP machine and P9, HDAT will provide it always. * - * Choosing the second level of affinity is model specific * unfortunately. Current POWER8E models should use the DCM * as a second level of NUMA. * * If there is a way to obtain this information from the FSP * that would be ideal, but for now hardwire our POWER8E setting. + * + * On P9 system we always use the PowerBus node ID */ if (PVR_TYPE(mfspr(SPR_PVR)) == PVR_TYPE_P8E) ref2 = 0x3; @@ -95,23 +97,23 @@ void add_chip_dev_associativity(struct dt_node *dev) { uint32_t chip_id = dt_get_chip_id(dev); struct proc_chip *chip = get_chip(chip_id); - uint32_t hw_cid, hw_mid; + uint32_t hw_cid, hw_mid, cn_id; if (!chip) return; - hw_cid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-card-id", 0); - hw_mid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-module-id", 0); + cn_id = get_chip_node_id(chip); + hw_cid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-card-id", cn_id); + hw_mid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-module-id", cn_id); dt_add_property_cells(dev, "ibm,associativity", 4, - get_chip_node_id(chip), - hw_cid, hw_mid, chip_id); + cn_id, hw_cid, hw_mid, chip_id); } void add_core_associativity(struct cpu_thread *cpu) { struct proc_chip *chip = get_chip(cpu->chip_id); - uint32_t hw_cid, hw_mid, core_id; + uint32_t hw_cid, hw_mid, core_id, cn_id; if (!chip) return; @@ -125,10 +127,10 @@ void add_core_associativity(struct cpu_thread *cpu) else return; - hw_cid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-card-id", 0); - hw_mid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-module-id", 0); + cn_id = get_chip_node_id(chip); + hw_cid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-card-id", cn_id); + hw_mid = dt_prop_get_u32_def(chip->devnode, "ibm,hw-module-id", cn_id); dt_add_property_cells(cpu->node, "ibm,associativity", 5, - get_chip_node_id(chip), - hw_cid, hw_mid, chip->id, core_id); + cn_id, hw_cid, hw_mid, chip->id, core_id); }