From patchwork Mon Feb 13 20:31:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shilpasri G Bhat X-Patchwork-Id: 728010 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vNHr52plgz9s0m for ; Wed, 15 Feb 2017 09:57:41 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vNHr523LbzDqHK for ; Wed, 15 Feb 2017 09:57:41 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vMcgX2xb2zDqBQ for ; Tue, 14 Feb 2017 07:32:56 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1DKUIwn040008 for ; Mon, 13 Feb 2017 15:32:54 -0500 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 28kk8msevt-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 13 Feb 2017 15:32:54 -0500 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 14 Feb 2017 06:32:49 +1000 Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id CA9AC2BB0055 for ; Tue, 14 Feb 2017 07:32:48 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1DKWetP31195146 for ; Tue, 14 Feb 2017 07:32:48 +1100 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v1DKWG6j001692 for ; Tue, 14 Feb 2017 07:32:16 +1100 Received: from oc4502181600.ibm.com ([9.77.202.18]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v1DKW3UA001127; Tue, 14 Feb 2017 07:32:12 +1100 From: Shilpasri G Bhat To: stewart@linux.vnet.ibm.com Date: Tue, 14 Feb 2017 02:01:41 +0530 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1487017902-14345-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> References: <1487017902-14345-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17021320-0004-0000-0000-000001E02D71 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17021320-0005-0000-0000-000009A8B15C Message-Id: <1487017902-14345-3-git-send-email-shilpa.bhat@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-13_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=3 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702130195 X-Mailman-Approved-At: Wed, 15 Feb 2017 09:57:20 +1100 Subject: [Skiboot] [PATCH V7 2/3] occ: Fix Pstate ordering for P9 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" In P9 the pstate values are positive. They are continuous set of unsigned integers [0 to +N] where Pmax is 0 and Pmin is N. The linear ordering of pstates for P9 has changed compared to P8. P8 has neagtive pstate values advertised as [0 to -N] where Pmax is 0 and Pmin is -N. This patch adds helper routines to abstract pstate comparison with pmax and adds sanity pstate limit checks. This patch also fixes pstate arithmetic by using labs(). Suggested-by: Gautham R. Shenoy Signed-off-by: Shilpasri G Bhat --- No changes from V6 hw/occ.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 88 insertions(+), 4 deletions(-) diff --git a/hw/occ.c b/hw/occ.c index ee76be6..9eb32b4 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -84,6 +84,40 @@ DEFINE_LOG_ENTRY(OPAL_RC_OCC_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_OCC, OPAL_CEC_HARDWARE, OPAL_UNRECOVERABLE_ERR_GENERAL, OPAL_NA); +/** + * cmp_pstates: Compares the given two pstates and determines which + * among them is associated with a higher pstate. + * + * @a,@b: The pstate ids of the pstates being compared. + * + * Returns: -1 : If pstate associated with @a is smaller than + * the pstate associated with @b. + * 0 : If pstates associated with @a and @b are equal. + * 1 : If pstate associated with @a is greater than + * the pstate associated with @b. + */ +static int (*cmp_pstates)(int a, int b); + +static int cmp_positive_pstates(int a, int b) +{ + if (a > b) + return -1; + else if (a < b) + return 1; + + return 0; +} + +static int cmp_negative_pstates(int a, int b) +{ + if (a < b) + return -1; + else if (a > b) + return 1; + + return 0; +} + /* Check each chip's HOMER/Sapphire area for PState valid bit */ static bool wait_for_all_occ_init(void) { @@ -214,15 +248,38 @@ static bool add_cpu_pstate_properties(s8 *pstate_nom) return false; } + /* + * Workload-Optimized-Frequency(WOF) or Ultra-Turbo is supported + * from version 2 onwards. If WOF is disabled then, the max + * ultra_turbo pstate will be equal to max turbo pstate. + */ if (occ_data->version > 1 && - occ_data->pstate_ultra_turbo > occ_data->pstate_turbo) + cmp_pstates(occ_data->pstate_ultra_turbo, + occ_data->pstate_turbo) > 0) ultra_turbo_en = true; else ultra_turbo_en = false; pmax = ultra_turbo_en ? occ_data->pstate_ultra_turbo : occ_data->pstate_turbo; - nr_pstates = pmax - occ_data->pstate_min + 1; + + /* Sanity check for pstate limits */ + if (cmp_pstates(occ_data->pstate_min, pmax) > 0) { + /** + * @fwts-label OCCInvalidPStateLimits + * @fwts-advice The min pstate is greater than the + * max pstate, this could be due to corrupted/invalid + * data in OCC-OPAL shared memory region. So OPAL has + * not added pstates to device tree. This means that + * CPU Frequency management will not be functional in + * the host. + */ + prlog(PR_ERR, "OCC: Invalid Pstate Limits. Pmin(%d) > Pmax (%d)\n", + occ_data->pstate_min, pmax); + return false; + } + + nr_pstates = labs(pmax - occ_data->pstate_min) + 1; prlog(PR_DEBUG, "OCC: Min %d Nom %d Max %d Nr States %d\n", occ_data->pstate_min, occ_data->pstate_nom, pmax, nr_pstates); @@ -319,15 +376,31 @@ static bool add_cpu_pstate_properties(s8 *pstate_nom) dt_core_max[i] = occ_data->core_max[i]; } + /* + * OCC provides pstate table entries in continuous descending order. + * Parse the pstate table to skip pstate_ids that are greater + * than Pmax. If a pstate_id is equal to Pmin then add it to + * the list and break from the loop as this is the last valid + * element in the pstate table. + */ for (i = 0, j = 0; i < MAX_PSTATES && j < nr_pstates; i++) { - if (occ_data->pstates[i].id > pmax || - occ_data->pstates[i].id < occ_data->pstate_min) + if (cmp_pstates(occ_data->pstates[i].id, pmax) > 0) continue; + dt_id[j] = occ_data->pstates[i].id; dt_freq[j] = occ_data->pstates[i].freq_khz / 1000; dt_vdd[j] = occ_data->pstates[i].vdd; dt_vcs[j] = occ_data->pstates[i].vcs; j++; + + if (occ_data->pstates[i].id == occ_data->pstate_min) + break; + } + + if (j != nr_pstates) { + prerror("OCC: Expected pstates(%d) is not equal to parsed pstates(%d)\n", + nr_pstates, j); + goto out_free_vcs; } /* Add the device-tree entries */ @@ -533,6 +606,17 @@ void occ_pstates_init(void) if (occ_pstates_initialized) return; + switch (proc_gen) { + case proc_gen_p8: + cmp_pstates = cmp_negative_pstates; + break; + case proc_gen_p9: + cmp_pstates = cmp_positive_pstates; + break; + default: + return; + } + chip = next_chip(NULL); if (!chip->homer_base) { log_simple_error(&e_info(OPAL_RC_OCC_PSTATE_INIT),