From patchwork Wed Jan 11 00:31:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 713498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tyqZx70JZz9t1B for ; Wed, 11 Jan 2017 11:31:53 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tyqZx5QTWzDqNb for ; Wed, 11 Jan 2017 11:31:53 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tyqZS4NFMzDqLx for ; Wed, 11 Jan 2017 11:31:28 +1100 (AEDT) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id v0B0TCbH120251 for ; Tue, 10 Jan 2017 19:31:26 -0500 Received: from e23smtp04.au.ibm.com (e23smtp04.au.ibm.com [202.81.31.146]) by mx0a-001b2d01.pphosted.com with ESMTP id 27w6u87hqg-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 10 Jan 2017 19:31:26 -0500 Received: from localhost by e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 11 Jan 2017 10:31:21 +1000 Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id F40723578056 for ; Wed, 11 Jan 2017 11:31:20 +1100 (EST) Received: from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v0B0VNRn44892246 for ; Wed, 11 Jan 2017 11:31:23 +1100 Received: from d23av05.au.ibm.com (localhost [127.0.0.1]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v0B0VK90005907 for ; Wed, 11 Jan 2017 11:31:20 +1100 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v0B0VKm5005892; Wed, 11 Jan 2017 11:31:20 +1100 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id BBE20A0222; Wed, 11 Jan 2017 11:31:19 +1100 (AEDT) Received: from gwshan.ozlabs.ibm.com (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id AFAB5E3D02; Wed, 11 Jan 2017 11:31:19 +1100 (AEDT) Received: by gwshan.ozlabs.ibm.com (Postfix, from userid 1000) id A6D05AC2906; Wed, 11 Jan 2017 11:31:19 +1100 (AEDT) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Wed, 11 Jan 2017 11:31:11 +1100 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484094678-27021-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1484094678-27021-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17011100-0012-0000-0000-000002024880 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17011100-0013-0000-0000-000006C9CC35 Message-Id: <1484094678-27021-2-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-10_21:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701110006 Subject: [Skiboot] [PATCH 1/8] platforms/astbmc: Support SMC's P8DNU X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hankmax0000@gmail.com, williel@supermicro.com.tw MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This supports superMicro's P8DNU platform. Signed-off-by: Willie Liauw Signed-off-by: Hank Chang Signed-off-by: Gavin Shan --- platforms/astbmc/Makefile.inc | 3 +- platforms/astbmc/p8dnu.c | 345 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 347 insertions(+), 1 deletion(-) create mode 100644 platforms/astbmc/p8dnu.c diff --git a/platforms/astbmc/Makefile.inc b/platforms/astbmc/Makefile.inc index 0830b3e..22c918d 100644 --- a/platforms/astbmc/Makefile.inc +++ b/platforms/astbmc/Makefile.inc @@ -1,6 +1,7 @@ SUBDIRS += $(PLATDIR)/astbmc -ASTBMC_OBJS = palmetto.o habanero.o firestone.o p8dtu.o garrison.o barreleye.o pnor.o common.o slots.o +ASTBMC_OBJS = palmetto.o habanero.o firestone.o p8dtu.o p8dnu.o \ + garrison.o barreleye.o pnor.o common.o slots.o ASTBMC = $(PLATDIR)/astbmc/built-in.o $(ASTBMC): $(ASTBMC_OBJS:%=$(PLATDIR)/astbmc/%) diff --git a/platforms/astbmc/p8dnu.c b/platforms/astbmc/p8dnu.c new file mode 100644 index 0000000..3590a7b --- /dev/null +++ b/platforms/astbmc/p8dnu.c @@ -0,0 +1,345 @@ +/* Copyright 2013-2014 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "astbmc.h" + +static const struct slot_table_entry p8dnu_phb0_0_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "UIO SLOT1", + }, + { .etype = st_end }, +}; + + +static const struct slot_table_entry p8dnu_plx_slots_00[] = { + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(1, 0), + .name = "Onboard_SATA", + }, + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(2, 0), + .name = "Slot Empty", + }, + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(8, 0), + .name = "Intel LAN", + }, + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(9, 0), + .name = "Onboard VGA", + }, + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(0xa, 0), + .name = "Onboard USB", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_plx_up_00[] = { + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(0, 0), + .children = p8dnu_plx_slots_00, + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb0_1_slot[] = { + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(0, 0), + .name = "Backplane PLX VS0", + .children = p8dnu_plx_up_00, + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb0_2_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "GPU1", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb0_3_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "GPU2", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_npu0_slots[] = { + { + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(0), + .name = "GPU2", + }, + { + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(1), + .name = "GPU1", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb1_0_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "WIO SLOT1", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_plx_slots[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(5, 0), + .name = "RSC-R1UW-E8R SLOT1", + }, + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0xc, 0), + .name = "WIO SLOT3", + }, + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0xd, 0), + .name = "WIO SLOT2", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_plx_up[] = { + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(0, 0), + .children = p8dnu_plx_slots, + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb1_1_slot[] = { + { + .etype = st_builtin_dev, + .location = ST_LOC_DEVFN(0, 0), + .name = "Backplane PLX VS1", + .children = p8dnu_plx_up, + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb1_2_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "GPU3", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb1_3_slot[] = { + { + .etype = st_pluggable_slot, + .location = ST_LOC_DEVFN(0, 0), + .name = "GPU4", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_npu1_slots[] = { + { + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(0), + .name = "GPU4", + }, + { + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(1), + .name = "GPU3", + }, + { .etype = st_end }, +}; + +static const struct slot_table_entry p8dnu_phb_table[] = { + { + .etype = st_phb, + .location = ST_LOC_PHB(0, 0), + .children = p8dnu_phb0_0_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(0, 1), + .children = p8dnu_phb0_1_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(0, 2), + .children = p8dnu_phb0_2_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(0, 3), + .children = p8dnu_phb0_3_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(0, 4), + .children = p8dnu_npu0_slots, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(1, 0), + .children = p8dnu_phb1_0_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(1, 1), + .children = p8dnu_phb1_1_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(1, 2), + .children = p8dnu_phb1_2_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(1, 3), + .children = p8dnu_phb1_3_slot, + }, + { + .etype = st_phb, + .location = ST_LOC_PHB(1, 4), + .children = p8dnu_npu1_slots, + }, + { .etype = st_end }, +}; + +#define NPU_BASE 0x8013c00 +#define NPU_SIZE 0x2c +#define NPU_INDIRECT0 0x8000000008010c3f +#define NPU_INDIRECT1 0x8000000008010c7f + +static void create_link(struct dt_node *npu, int group, int index) +{ + struct dt_node *link; + uint32_t lane_mask; + uint64_t phy; + char namebuf[32]; + + snprintf(namebuf, sizeof(namebuf), "link@%x", index); + link = dt_new(npu, namebuf); + + dt_add_property_string(link, "compatible", "ibm,npu-link"); + dt_add_property_cells(link, "ibm,npu-link-index", index); + + if (index < 4) { + phy = NPU_INDIRECT0; + lane_mask = 0xff << (index * 8); + } else { + phy = NPU_INDIRECT1; + lane_mask = 0xff0000 >> (index - 3) * 8; + } + dt_add_property_u64s(link, "ibm,npu-phy", phy); + dt_add_property_cells(link, "ibm,npu-lane-mask", lane_mask); + dt_add_property_cells(link, "ibm,npu-group-id", group); +} + +static void dt_create_npu(void) +{ + struct dt_node *xscom, *npu; + char namebuf[32]; + + dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { + snprintf(namebuf, sizeof(namebuf), "npu@%x", NPU_BASE); + npu = dt_new(xscom, namebuf); + dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE); + dt_add_property_strings(npu, "compatible", "ibm,power8-npu"); + + /* Use the first available PHB index which is 4 given + * there are three normal PHBs. */ + dt_add_property_cells(npu, "ibm,phb-index", 4); + dt_add_property_cells(npu, "ibm,npu-index", 0); + dt_add_property_cells(npu, "ibm,npu-links", 4); + + /* On p8dnu we have 2 links per GPU device. These are + * grouped together as per the slot tables above. */ + create_link(npu, 0, 0); + create_link(npu, 0, 1); + create_link(npu, 1, 4); + create_link(npu, 1, 5); + } +} + +static bool p8dnu_probe(void) +{ + if (!dt_node_is_compatible(dt_root, "supermicro,p8dnu")) + return false; + + /* Lot of common early inits here */ + astbmc_early_init(); + + /* + * Override external interrupt policy -> send to Linux + * + * On Naples, we get LPC interrupts via the built-in LPC + * controller demuxer, not an external CPLD. The external + * interrupt is for other uses, such as the TPM chip, we + * currently route it to Linux, but we might change that + * later if we decide we need it. + */ + psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_LINUX); + + /* Fixups until HB get the NPU bindings */ + dt_create_npu(); + + slot_table_init(p8dnu_phb_table); + + return true; +} + +DECLARE_PLATFORM(p8dnu) = { + .name = "P8DNU", + .probe = p8dnu_probe, + .init = astbmc_init, + .pci_get_slot_info = slot_table_get_slot_info, + .cec_power_down = astbmc_ipmi_power_down, + .cec_reboot = astbmc_ipmi_reboot, + .elog_commit = ipmi_elog_commit, + .start_preload_resource = flash_start_preload_resource, + .resource_loaded = flash_resource_loaded, + .exit = ipmi_wdt_final_reset, + .terminate = ipmi_terminate, +};