@@ -625,6 +625,16 @@ static void per_thread_sanity_checks(void)
struct cpu_thread *cpu = this_cpu();
+ /**
+ * @fwts-label NonZeroHRMOR
+ * @fwts-advice The contents of the hypervisor real mode offset register
+ * (HRMOR) is bitwise orded with the address of any hypervisor real mode
+ * (i.e Skiboot) memory accesses. Skiboot does not support operating
+ * with a non-zero HRMOR and setting it will break some things (e.g
+ * XSCOMs) in hard-to-debug ways.
+ */
+ assert(mfspr(SPR_HRMOR) == 0);
+
/**
* @fwts-label UnknownSecondary
* @fwts-advice The boot CPU attampted to call in a secondary thread
* without initialising the corresponding cpu_thread structure. This may
@@ -67,6 +67,7 @@
#define SPR_SPURR 0x134 /* RW: Scaled Processor Utilization Resource */
#define SPR_PURR 0x135 /* RW: Processor Utilization Resource reg */
#define SPR_HDEC 0x136 /* RW: Hypervisor Decrementer */
+#define SPR_HRMOR 0x139 /* RW: Hypervisor Real Mode Offset reg */
#define SPR_HSRR0 0x13a /* RW: HV Exception save/restore reg 0 */
#define SPR_HSRR1 0x13b /* RW: HV Exception save/restore reg 1 */
#define SPR_TFMR 0x13d
We have only ever supported running with HRMOR = 0. Having a non-zero HRMOR causes all real mode accesses to have the value of HRMOR bitwise ORed into the address that would have been accessed. This causes issues when accessing MMIO registers such as the XSCOMs. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> --- core/init.c | 10 ++++++++++ include/processor.h | 1 + 2 files changed, 11 insertions(+)