From patchwork Fri Oct 2 06:42:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 525406 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D3DA0140316 for ; Fri, 2 Oct 2015 16:43:09 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 9162B1A05AC for ; Fri, 2 Oct 2015 16:43:09 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 265E21A04D3 for ; Fri, 2 Oct 2015 16:43:05 +1000 (AEST) Received: from /spool/local by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 2 Oct 2015 16:43:01 +1000 X-Helo: d23dlp03.au.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 3EC37357804F for ; Fri, 2 Oct 2015 16:43:01 +1000 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t926gmaw41287870 for ; Fri, 2 Oct 2015 16:42:57 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t926gRS9000846 for ; Fri, 2 Oct 2015 16:42:27 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t926gRBW000579; Fri, 2 Oct 2015 16:42:27 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 89A4DA028C; Fri, 2 Oct 2015 16:42:03 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 7B300E45F4; Fri, 2 Oct 2015 16:42:03 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 534B3941D2C; Fri, 2 Oct 2015 16:42:03 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 2 Oct 2015 16:42:02 +1000 Message-Id: <1443768122-13365-1-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15100206-0005-0000-0000-000002899EA9 Subject: [Skiboot] [PATCH] PHB3: Fix unexpected ER (all) on errinjct by PCI config X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cjlarson@us.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This issue was found on SRIOV VFs initially and then I checked with Chad Larson who put much efforts to sort it out. As more experiments I did, the issue isn't limited to SRIOV VFs. That means the isue can be seen on non-SRIOV adapter as well: Firstly, I ensure that outbound request discard interrupt (bit#12) is enabled in PCI Express Port Interrupt Enable Register (offset: 0x558). Then injecting error to root complex by PAPR Error Injection Registers with PCI config read. Eventually, all (256) PEs are frozen. After clearing the bit, the target PE#0 is frozen as expected. As Chad pointed, the interrupt ("outbound request discard") is always raised during the error injection, which is translated to UTL's primary interrupt to freeze all (256) PEs. This drops bit#12 of PCI Express Port Interrupt Enable Register to avoid the UTL's primary interrupt caused by outbound request discard, in order to avoid freezing all (256) PEs during error injection via PCI config read. Signed-off-by: Gavin Shan --- hw/phb3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index 71c64be..d57cbd9 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2031,7 +2031,7 @@ static void phb3_setup_for_link_up(struct phb3 *p) /* Clear spurrious errors and enable PCIE port interrupts */ out_be64(p->regs + UTL_PCIE_PORT_STATUS, 0xffdfffffffffffff); - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad5a800000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad52800000000000); /* Mark link up */ p->has_link = true; @@ -3834,7 +3834,7 @@ static void phb3_init_utl(struct phb3 *p) out_be64(p->regs + UTL_PCIE_PORT_ERROR_SEV, 0x5039000000000000); if (p->has_link) - out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad5a800000000000); + out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad52800000000000); else out_be64(p->regs + UTL_PCIE_PORT_IRQ_EN, 0xad42800000000000);