From patchwork Mon Apr 27 06:26:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 464804 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EED2A140318 for ; Mon, 27 Apr 2015 16:27:56 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id D5CA21A08E2 for ; Mon, 27 Apr 2015 16:27:56 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 6AED31A08A6 for ; Mon, 27 Apr 2015 16:27:38 +1000 (AEST) Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 27 Apr 2015 16:27:33 +1000 Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 75E7E2CE8040 for ; Mon, 27 Apr 2015 16:27:33 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t3R6RPRo46858358 for ; Mon, 27 Apr 2015 16:27:33 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t3R6QxZS009798 for ; Mon, 27 Apr 2015 16:27:00 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t3R6QxGF009151; Mon, 27 Apr 2015 16:26:59 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.253.15]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 9FE1EA0272; Mon, 27 Apr 2015 16:26:36 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 2FB8716AA01; Mon, 27 Apr 2015 16:26:36 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 03C279421F8; Mon, 27 Apr 2015 16:26:35 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Mon, 27 Apr 2015 16:26:21 +1000 Message-Id: <1430115993-20560-4-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1430115993-20560-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1430115993-20560-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15042706-0009-0000-0000-0000014E2372 Subject: [Skiboot] [PATCH v5 03/15] hw/p8-i2c: Allow to disable timeout X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When changing power supply status to PCI slot during bootup, which is done through I2C requests, the interrupt stuff isn't working yet and we have to invoke polling timers proactively at fixed interval. Unfortunately, the I2C master's timeout is usually very short and we will encounter master timeout on the first poll at system bootup time. In order to avoid the problem, the patch allows users to disable the timeout by setting I2C request's timeout set (uint64_t)(-1). Signed-off-by: Gavin Shan --- hw/p8-i2c.c | 26 ++++++++++++++++++++------ include/i2c.h | 9 +++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 3d5b9d4..5450b89 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -367,10 +367,14 @@ static int p8_i2c_prog_mode(struct p8_i2c_master_port *port, bool enhanced_mode) static void p8_i2c_complete_request(struct p8_i2c_master *master, struct i2c_request *req, int ret) { + struct p8_i2c_request *request = + container_of(req, struct p8_i2c_request, req); + /* We only complete the current top level request */ assert(req == list_top(&master->req_list, struct i2c_request, link)); - cancel_timer_async(&master->timeout); + if (request->timeout != (uint64_t)(-1)) + cancel_timer_async(&master->timeout); list_del(&req->link); master->state = state_idle; unlock(&master->lock); @@ -925,11 +929,11 @@ static int p8_i2c_start_request(struct p8_i2c_master *master, now = schedule_timer(&master->poller, master->poll_interval); /* Calculate and start timeout */ - tbytes = req->rw_len + req->offset_bytes + 2; - request->timeout = now + tbytes * master->byte_timeout; - - /* Start the timeout */ - schedule_timer_at(&master->timeout, request->timeout); + if (request->timeout != (uint64_t)(-1)) { + tbytes = req->rw_len + req->offset_bytes + 2; + request->timeout = now + tbytes * master->byte_timeout; + schedule_timer_at(&master->timeout, request->timeout); + } return OPAL_SUCCESS; } @@ -998,6 +1002,15 @@ static void p8_i2c_free_request(struct i2c_request *req) free(request); } +static void p8_i2c_set_request_timeout(struct i2c_request *req, + uint64_t timeout) +{ + struct p8_i2c_request *request = + container_of(req, struct p8_i2c_request, req); + + request->timeout = timeout; +} + static inline uint32_t p8_i2c_get_bit_rate_divisor(uint32_t lb_freq, uint32_t bus_speed) { @@ -1264,6 +1277,7 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) port->bus.queue_req = p8_i2c_queue_request; port->bus.alloc_req = p8_i2c_alloc_request; port->bus.free_req = p8_i2c_free_request; + port->bus.set_req_timeout = p8_i2c_set_request_timeout; i2c_add_bus(&port->bus); /* Add OPAL properties to the bus node */ diff --git a/include/i2c.h b/include/i2c.h index dea0644..5963726 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -26,6 +26,8 @@ struct i2c_bus { int (*queue_req)(struct i2c_request *req); struct i2c_request *(*alloc_req)(struct i2c_bus *bus); void (*free_req)(struct i2c_request *req); + void (*set_req_timeout)(struct i2c_request *req, + uint64_t timeout); }; /* @@ -80,6 +82,13 @@ static inline int i2c_queue_req(struct i2c_request *req) return req->bus->queue_req(req); } +static inline void i2c_set_req_timeout(struct i2c_request *req, + uint64_t timeout) +{ + if (req->bus->set_req_timeout) + req->bus->set_req_timeout(req, timeout); +} + /* P8 implementation details */ extern void p8_i2c_init(void); extern void p8_i2c_interrupt(uint32_t chip_id);