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[2/2] hw/phb4: Verify AER support before initialising AER regs

Message ID 20200828043055.1563069-2-oohall@gmail.com
State Accepted
Headers show
Series [1/2] hw/phb4: Actually enable error reporting | expand

Commit Message

Oliver O'Halloran Aug. 28, 2020, 4:30 a.m. UTC
Check the AER capability offset pointer is non-zero before enabling the
AER messages. If the device doesn't support AER we end up writing
garbage to config offset 0x0 + PCIECAP_AER_CAPCTL, or 0x18. For a normal
device this is one of the BARs so this doesn't do much, but for a bridge
this results in overriding:

	0x18 - The primary bus number
	0x19 - The secondary bus number
	0x1A - The subordinate bus number
	0x1B - The latency timer

0x1B is hardwired to zero for PCIe devices, but overwriting the bus
number register can cause issues with routing of config space accesses.
It's worth pointing out that we write actual values for the secondary
and subordinate bus numbers before scanning the secondary bus, but the
primary bus number is never restored.

Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
 hw/phb4.c | 3 +++
 1 file changed, 3 insertions(+)
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diff --git a/hw/phb4.c b/hw/phb4.c
index 328621917667..17a233f39ff1 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -788,6 +788,9 @@  static void phb4_endpoint_init(struct phb *phb,
 	pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16);
 	/* Enable ECRC generation and check */
+	if (!aercap)
+		return;
 	pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32);