From patchwork Thu Apr 23 17:54:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1275956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 497Q212SsMz9sSX for ; Fri, 24 Apr 2020 03:55:21 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 497Q204FyqzDqjL for ; Fri, 24 Apr 2020 03:55:20 +1000 (AEST) X-Original-To: skiboot-stable@lists.ozlabs.org Delivered-To: skiboot-stable@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 497Q1q3dRGzDqgV; Fri, 24 Apr 2020 03:55:10 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 03NHW9K9029953; Thu, 23 Apr 2020 13:55:08 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 30jrc622bf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2020 13:55:08 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 03NHp4B7011131; Thu, 23 Apr 2020 17:55:06 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma04ams.nl.ibm.com with ESMTP id 30fs65831s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2020 17:55:06 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 03NHrsNW60948810 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 23 Apr 2020 17:53:54 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B2A1911C058; Thu, 23 Apr 2020 17:55:01 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 70C9B11C04C; Thu, 23 Apr 2020 17:55:01 +0000 (GMT) Received: from pic2.home (unknown [9.145.168.9]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 23 Apr 2020 17:55:01 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Thu, 23 Apr 2020 19:54:43 +0200 Message-Id: <20200423175443.213832-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.25.3 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-23_13:2020-04-23, 2020-04-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxscore=0 suspectscore=1 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004230132 Subject: [Skiboot-stable] [PATCH v2] platform/mihawk: Tune equalization settings for opencapi X-BeenThere: skiboot-stable@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Patches, review, and discussion for stable releases of skiboot" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, skiboot-stable@lists.ozlabs.org, chhank@tw.ibm.com, andrew.donnellan@au1.ibm.com, joy_chu@wistron.com Errors-To: skiboot-stable-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot-stable" The Bittware 250SOC adapter on Mihawk was showing a high count of CRC errors on one of the opencapi slots. The PHY team suggested new equalization settings to correct the errors. All existing adapters have been tested on mihawk to make sure the settings are compatible. However, the new settings should not be used on platforms other than mihawk. The changes specific to mihawk are: - Update the tx_ffe_pre_coeff and tx_ffe_post_coeff input parameters used during zcal - turn off the tx_ffe_boost parameter through scom Signed-off-by: Frederic Barrat Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x Reviewed-by: Andrew Donnellan --- Vasant, Oliver: this is for mihawk and should not have any side effect on other plaforms. At this point, I'm thoroughly confused whether it should go to the skiboot-op940.x branch, as I'm hearing conflicting signals. In any case, it should go to master for our own good and be able to use our lab systems. Time will sort out the skiboot-op940.x status. Changelog: v2: avoid globals (Andrew) hw/npu2-hw-procedures.c | 23 +++++++++++++++++++---- include/platform.h | 7 +++++++ platforms/astbmc/mihawk.c | 7 +++++++ 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 6236380a..fb88dfdf 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -78,6 +78,7 @@ static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_DONE = {0x3c1, 50, 1}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_ERROR = {0x3c1, 51, 1}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_N = {0x3c3, 48, 9}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_P = {0x3c5, 48, 9}; +static struct npu2_phy_reg NPU2_PHY_TX_FFE_BOOST_EN = {0x34b, 59, 1}; static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_EN = {0x34d, 51, 5}; static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_SELECT = {0x34d, 56, 5}; static struct npu2_phy_reg NPU2_PHY_TX_NSEG_PRE_EN = {0x34f, 51, 5}; @@ -533,6 +534,8 @@ static uint32_t therm_with_half(uint32_t dec, uint8_t width) static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev) { int p_value, n_value; + int ffe_pre_coeff = FFE_PRE_COEFF; + int ffe_post_coeff = FFE_POST_COEFF; uint32_t zcal_n; uint32_t zcal_p; uint32_t p_main_enable = MAIN_X2_MAX; @@ -564,9 +567,15 @@ static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev) (zcal_p < ZCAL_MIN) || (zcal_p > ZCAL_MAX)) return PROCEDURE_COMPLETE | PROCEDURE_FAILED; + if (ndev->type == NPU2_DEV_TYPE_OPENCAPI && + platform.ocapi->phy_setup) { + ffe_pre_coeff = platform.ocapi->phy_setup->tx_ffe_pre_coeff; + ffe_post_coeff = platform.ocapi->phy_setup->tx_ffe_post_coeff; + } + p_value = zcal_p - TOTAL_X2_MAX; - p_precursor_select = (p_value * FFE_PRE_COEFF)/128; - p_postcursor_select = (p_value * FFE_POST_COEFF)/128; + p_precursor_select = (p_value * ffe_pre_coeff)/128; + p_postcursor_select = (p_value * ffe_post_coeff)/128; margin_pu_select = (p_value * MARGIN_RATIO)/256; if (p_value % 2) { @@ -587,8 +596,8 @@ static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev) } n_value = zcal_n - TOTAL_X2_MAX; - n_precursor_select = (n_value * FFE_PRE_COEFF)/128; - n_postcursor_select = (n_value * FFE_POST_COEFF)/128; + n_precursor_select = (n_value * ffe_pre_coeff)/128; + n_postcursor_select = (n_value * ffe_post_coeff)/128; margin_pd_select = (p_value * MARGIN_RATIO)/256; if (n_value % 2) { @@ -1020,6 +1029,12 @@ void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev) void npu2_opencapi_phy_init(struct npu2_dev *dev) { + if (platform.ocapi->phy_setup) { + OCAPIINF(dev, "Enabling platform-specific PHY setup\n"); + phy_write(dev, &NPU2_PHY_TX_FFE_BOOST_EN, + platform.ocapi->phy_setup->tx_ffe_boost_en); + } + run_procedure(dev, 5); /* procedure_phy_tx_zcal */ /* * This is only required for OpenCAPI - Hostboot tries to set this diff --git a/include/platform.h b/include/platform.h index 6aa263ae..ef93278b 100644 --- a/include/platform.h +++ b/include/platform.h @@ -47,6 +47,12 @@ struct bmc_platform { const struct bmc_sw_config *sw; }; +struct ocapi_phy_setup { + int tx_ffe_pre_coeff; + int tx_ffe_post_coeff; + int tx_ffe_boost_en; +}; + /* OpenCAPI platform-specific I2C information */ struct platform_ocapi { uint8_t i2c_engine; /* I2C engine number */ @@ -64,6 +70,7 @@ struct platform_ocapi { bool odl_phy_swap; /* Swap ODL1 to use brick 2 rather than * brick 1 lanes */ const char *(*ocapi_slot_label)(uint32_t chip_id, uint32_t brick_index); + const struct ocapi_phy_setup *phy_setup; }; struct dt_node; diff --git a/platforms/astbmc/mihawk.c b/platforms/astbmc/mihawk.c index 8971b407..f3669ff3 100644 --- a/platforms/astbmc/mihawk.c +++ b/platforms/astbmc/mihawk.c @@ -142,6 +142,12 @@ static const char *mihawk_ocapi_slot_label(uint32_t chip_id, return name; } +static const struct ocapi_phy_setup mihawk_phy = { + .tx_ffe_pre_coeff = 0x3, + .tx_ffe_post_coeff = 0x14, + .tx_ffe_boost_en = 0, +}; + static const struct platform_ocapi mihawk_ocapi = { .i2c_engine = 1, .i2c_port = 4, @@ -157,6 +163,7 @@ static const struct platform_ocapi mihawk_ocapi = { .i2c_presence_brick5 = 0, /* unused */ .odl_phy_swap = true, .ocapi_slot_label = mihawk_ocapi_slot_label, + .phy_setup = &mihawk_phy, }; static const struct slot_table_entry P1E1A_x8_PLX8748_RiserA_down[] = {