From patchwork Wed Jul 8 22:29:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Yeryomin X-Patchwork-Id: 493177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-la0-x23f.google.com (mail-la0-x23f.google.com [IPv6:2a00:1450:4010:c03::23f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3C7241402B5 for ; Thu, 9 Jul 2015 08:29:45 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlegroups.com header.i=@googlegroups.com header.b=RA2X28R8; dkim-atps=neutral Received: by laer2 with SMTP id r2sf53865003lae.0 for ; Wed, 08 Jul 2015 15:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=20120806; h=to:subject:mime-version:content-type:date:from:cc:in-reply-to :references:message-id:user-agent:x-original-sender :x-original-authentication-results:reply-to:precedence:mailing-list :list-id:x-spam-checked-in-group:list-post:list-help:list-archive :sender:list-subscribe:list-unsubscribe; bh=bOEjwEA0WB7Kmz5QUrlYXeYXvOycHXO5USPVAe7NBsE=; b=RA2X28R8GpAIhZ4RM+MkD+R9PsZGpx8z6/cStYn1ury9dE9XHk0VsG5QzqbC2xypRi 3h3X4656sij7UH7bhfNgJzG0Y6npaKH7+0tAa8qSP4enUlHuV6r86JWxZGwT+kvlvFLW JZn2C+kpA1TZM3UfCkXMeOjcajUKRN+nM1LxgzMShopWu1pcZKp9GZp0tGmVldZd69ib EzkeXc35hNDm9RW0XmvOFVb+tB7WSQa5uCbnO9oup44LuIRuVE+vVin5zQKyXwnTPZCX 2zdPvPa/vaHx8VrOK+L/u1shPHzvmEDUkIV5usQxlJrajjgt+ZuECHSqtaZsvoR+xLoH Evjw== X-Received: by 10.152.7.104 with SMTP id i8mr157382laa.31.1436394581468; Wed, 08 Jul 2015 15:29:41 -0700 (PDT) X-BeenThere: rtc-linux@googlegroups.com Received: by 10.152.6.202 with SMTP id d10ls1042181laa.69.gmail; Wed, 08 Jul 2015 15:29:40 -0700 (PDT) X-Received: by 10.112.26.5 with SMTP id h5mr6081564lbg.4.1436394580753; Wed, 08 Jul 2015 15:29:40 -0700 (PDT) Received: from mail.pbx.lv ([213.175.90.140]) by gmr-mx.google.com with ESMTP id h8si108231lbd.3.2015.07.08.15.29.40 for ; Wed, 08 Jul 2015 15:29:40 -0700 (PDT) Received-SPF: neutral (google.com: 213.175.90.140 is neither permitted nor denied by best guess record for domain of roman@advem.lv) client-ip=213.175.90.140; Received: by mail.pbx.lv (MailSystem, from userid 80) id BE544C11A8; Thu, 9 Jul 2015 01:29:39 +0300 (EEST) To: Arnd Bergmann Subject: [rtc-linux] Re: [1/2] RTC: Add core rtc support for Gemini Soc devices MIME-Version: 1.0 Date: Thu, 09 Jul 2015 01:29:39 +0300 From: Roman Yeryomin Cc: linux-arm-kernel@lists.infradead.org, Felix Fietkau , rtc-linux@googlegroups.com, Linus Walleij , linux-kernel@vger.kernel.org, Alexandre Belloni , Russell King , Hans Ulli Kroll In-Reply-To: <2131951.l0j0CIttAZ@wuerfel> References: <1292339307-14336-2-git-send-email-ulli.kroll@googlemail.com> <2349062.9v3Zz7HPLu@wuerfel> <0701f75c1c42f74fd58845bc0ed41c38@advem.lv> <2131951.l0j0CIttAZ@wuerfel> Message-ID: X-Sender: roman@advem.lv User-Agent: Roundcube Webmail/1.0.1 X-Original-Sender: roman@advem.lv X-Original-Authentication-Results: gmr-mx.google.com; spf=neutral (google.com: 213.175.90.140 is neither permitted nor denied by best guess record for domain of roman@advem.lv) smtp.mail=roman@advem.lv Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Spam-Checked-In-Group: rtc-linux@googlegroups.com X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , On 2015-05-08 19:08, Arnd Bergmann wrote: > On Thursday 07 May 2015 12:03:25 Roman Yeryomin wrote: >> On 2015-05-06 22:22, Arnd Bergmann wrote: >> > On Wednesday 06 May 2015 19:21:21 Roman Yeryomin wrote: >> >> >> >> > Thanks to point that, I'll merge that one which seems clean enough: >> >> > http://git.openwrt.org/?p=openwrt.git;a=blob;f=target/linux/gemini/files/drivers/rtc/rtc-gemini.c;h=587d8122b2fbb1230437eadcce4789a53aa60ee5;hb=4c637410a2a1ab45988e8ca6202554a502102039 >> >> >> >> For 3.18 (and up) to work on gemini 160-gemini-timers.patch is vital. >> >> Without that timers are broken and cpu is super slow. >> > >> > Do you know what part of the patch is the actual bug fix? We should >> > probably >> > merge that separately and mark it for stable backports, while the bulk >> > of that >> > patch seems to just rearrange code. >> > >> > Arnd >> >> Sorry, didn't try to extract the exact lines it but I guess it's that >> part which touches the scheduler clock code. >> Because without that patch sched clock runs at 100Hz instead of 25MHz. >> I can dive into this deeper if you want, I just didn't see the need. > > I think that would be helpful, yes. > OK, here are the minimal changes required (see attachment). Tested on 4.1.1 Let me know if you want me to submit it in some other way. Regards, Roman Reviewed-by: Linus Walleij --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * Register definitions for the timers @@ -34,9 +35,17 @@ #define TIMER_3_CR_ENABLE (1 << 6) #define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_INT (1 << 8) +#define TIMER_1_CR_UPDOWN (1 << 9) +#define TIMER_2_CR_UPDOWN (1 << 10) +#define TIMER_3_CR_UPDOWN (1 << 11) static unsigned int tick_rate; +static u64 notrace gemini_read_sched_clock(void) +{ + return readl(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER3_BASE))); +} + static int gemini_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { @@ -155,14 +164,18 @@ void __init gemini_timer_init(void) */ setup_irq(IRQ_TIMER2, &gemini_timer_irq); - /* Enable and use TIMER1 as clock source */ - writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); - writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); - if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), - "TIMER1", tick_rate, 300, 32, + /* Enable and use TIMER3 as clock source */ + writel(0, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER3_BASE))); + writel(0, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER3_BASE))); + writel(0, TIMER_MATCH1(IO_ADDRESS(GEMINI_TIMER3_BASE))); + writel(0, TIMER_MATCH2(IO_ADDRESS(GEMINI_TIMER3_BASE))); + writel(TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN, + TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER3_BASE)), + "TIMER3", tick_rate, 300, 32, clocksource_mmio_readl_up)) pr_err("timer: failed to initialize gemini clock source\n"); + sched_clock_register(gemini_read_sched_clock, 32, tick_rate); /* Configure and register the clockevent */ clockevents_config_and_register(&gemini_clockevent, tick_rate,