From patchwork Wed Nov 4 15:36:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Clayton X-Patchwork-Id: 539994 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-ig0-x23b.google.com (mail-ig0-x23b.google.com [IPv6:2607:f8b0:4001:c05::23b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4E3161402D7 for ; Thu, 5 Nov 2015 02:37:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=googlegroups.com header.i=@googlegroups.com header.b=RhZx04gJ; dkim-atps=neutral Received: by igcg4 with SMTP id g4sf14281664igc.1 for ; Wed, 04 Nov 2015 07:37:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=20120806; h=mime-version:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references:x-original-sender :x-original-authentication-results:reply-to:content-type:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:sender:list-subscribe:list-unsubscribe; bh=LgW/LbP3SrcvSydWnk3RUnUsYy3oRFbnb9gbqAqNyis=; b=RhZx04gJ6n8t1VeF7Mc2+6ixtEYcV58NaD13d5cGPLh++/uKu9/PZTKo4ISuPHs6m4 S4//FvrZ0uUArfLxI1AfdGsuPmWvDx+YgtwR7S0rgokfD81AG8HraVG7Bu+r+HT1QUbE 8FevYoQwCzaO8ZR2aIwrjSBia2sZYoLl1zsSfUOaT9dEr9vmw+poC/ZVAuGfVN0p6p0P Br8A174dNpdEl4BC5rNLIw6v7B8C+sUeB23JTy1wvgvLSZcB1uUMHXyZI5IlhtX0pzQe 5qDQ+rPGsw1u5LExSKHoTo7a3iyEWJfgwpG28cFkvURsQVB3LOTCGC/iAZYke8KUnyU4 PgXQ== X-Received: by 10.50.67.179 with SMTP id o19mr97629igt.3.1446651424940; Wed, 04 Nov 2015 07:37:04 -0800 (PST) MIME-Version: 1.0 X-BeenThere: rtc-linux@googlegroups.com Received: by 10.107.135.204 with SMTP id r73ls443603ioi.51.gmail; Wed, 04 Nov 2015 07:37:04 -0800 (PST) X-Received: by 10.66.254.10 with SMTP id ae10mr1758973pad.32.1446651424487; Wed, 04 Nov 2015 07:37:04 -0800 (PST) Received: from mail-pa0-x22d.google.com (mail-pa0-x22d.google.com. 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[68.185.59.186]) by smtp.gmail.com with ESMTPSA id xm4sm2731317pab.27.2015.11.04.07.37.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Nov 2015 07:37:03 -0800 (PST) From: Joshua Clayton To: Alessandro Zummo , Alexandre Belloni Cc: rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org, Joshua Clayton Subject: [rtc-linux] [PATCH 1/9] rtc-pcf2123: Document all registers and useful bits Date: Wed, 4 Nov 2015 07:36:32 -0800 Message-Id: X-Mailer: git-send-email 2.5.0 In-Reply-To: References: In-Reply-To: References: X-Original-Sender: stillcompiling@gmail.com X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of stillcompiling@gmail.com designates 2607:f8b0:400e:c03::22d as permitted sender) smtp.mailfrom=stillcompiling@gmail.com; dmarc=pass (p=NONE dis=NONE) header.from=gmail.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Spam-Checked-In-Group: rtc-linux@googlegroups.com X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , Document all 16 registers in the pcf2123, as well as useful bit masks from the Control1 and seconds registers Signed-off-by: Joshua Clayton --- drivers/rtc/rtc-pcf2123.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c index d1953bb..7756210 100644 --- a/drivers/rtc/rtc-pcf2123.c +++ b/drivers/rtc/rtc-pcf2123.c @@ -47,6 +47,7 @@ #define DRV_VERSION "0.6" +/* REGISTERS */ #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ #define PCF2123_REG_SC (0x02) /* datetime */ @@ -56,7 +57,27 @@ #define PCF2123_REG_DW (0x06) #define PCF2123_REG_MO (0x07) #define PCF2123_REG_YR (0x08) - +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ +#define PCF2123_REG_ALRM_HR (0x0a) +#define PCF2123_REG_ALRM_DM (0x0b) +#define PCF2123_REG_ALRM_DW (0x0c) +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ +#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ +#define PCF2123_REG_CTDWN_TMR (0x0f) +#define PCF2123_REG_MAX (PCF2123_REG_CTDWN_TMR) + +/* PCF2123_REG_CTRL1 BITS */ +#define CTRL1_CLEAR (0x00) /* Clear */ +#define CTRL1_CORRECTION_INT (0x02) /* Correction Interrupt */ +#define CTRL1_12_HOUR (0x04) /* 12 hour time */ +#define CTRL1_STOP (0x20) /* Stop the clock */ +#define CTRL1_SW_RESET (0x58) /* Software reset */ +#define CTRL1_EXT_TEST (0x80) /* External Clock Test mode */ + +/* PCF2123_REG_SC BITS */ +#define OSC_HAS_STOPPED (0x80) /* Clock has been stopped */ + +/* READ/WRITE ADDRESS BITS */ #define PCF2123_SUBADDR (1 << 4) #define PCF2123_WRITE ((0 << 7) | PCF2123_SUBADDR) #define PCF2123_READ ((1 << 7) | PCF2123_SUBADDR)