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Sat, 27 Apr 2024 23:09:00 -0700 (PDT) Received: from localhost ([46.3.240.103]) by smtp.gmail.com with ESMTPSA id gu27-20020a056a004e5b00b006ee25097c2csm14608325pfb.103.2024.04.27.23.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 23:08:59 -0700 (PDT) From: Jingbao Qiu To: alexandre.belloni@bootlin.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: dlan@gentoo.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org, Jingbao Qiu , Krzysztof Kozlowski Subject: [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Date: Sun, 28 Apr 2024 14:08:47 +0800 Message-Id: <20240428060848.706573-2-qiujingbao.dlmu@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240428060848.706573-1-qiujingbao.dlmu@gmail.com> References: <20240428060848.706573-1-qiujingbao.dlmu@gmail.com> Precedence: bulk X-Mailing-List: linux-rtc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add RTC devicetree binding for Sophgo CV1800 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingbao Qiu --- .../bindings/rtc/sophgo,cv1800-rtc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml new file mode 100644 index 000000000000..b36b51a69166 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/sophgo,cv1800-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + Real Time Clock (RTC) is an independently powered module + within the chip, which includes a 32KHz oscillator and a + Power On Reset/POR submodule. It can be used for time display + and timed alarm generation. In addition, the hardware state + machine provides triggering and timing control for chip + power on, off, and reset. + +maintainers: + - Jingbao Qiu + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: sophgo,cv1800-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + rtc@5025000 { + compatible = "sophgo,cv1800-rtc"; + reg = <0x5025000 0x2000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + };