| Message ID | 20231103125106.78220-2-menin@carlosaurelio.net |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v2,1/2] rtc: add pcf85053a | expand |
On 03/11/2023 13:51, Carlos Menin wrote: > Add YAML bindings for NXP's PCF85053A RTC chip. > > Signed-off-by: Carlos Menin <menin@carlosaurelio.net> > Reviewed-by: Sergio Prado <sergio.prado@e-labworks.com> Thank you for your patch. There is something to discuss/improve. > + quartz-load-femtofarads: > + description: > + The capacitive load of the crystal, expressed in femto Farad (fF). > + enum: [6000, 7000, 12500] > + default: 12500 > + > + nxp,quartz-drive-control: > + description: > + The oscillator is designed to be used with quartz with a series resistance > + up to 100 kOhms. This covers the typical range of 32.768 kHz quartz > + crystals. A low drive mode is available for low series resistance quartz > + (up to 60 kOhms). This reduces the current consumption. For very high > + series resistance quartz (up to 500 kOhms), there is a high drive mode. > + Current consumption increases substantially in this mode. > + enum: [low, normal, high] > + default: normal > + > + nxp,low-jitter-mode: > + description: > + If set to true, will decrease the CLK output jitter, at the cost of > + increasing the current consumption. > + type: boolean > + default: false Drop this line. > + > + nxp,clk-inverted: > + description: > + Invert clock output. Normally, the low jitter mode reduces jitter on the > + rising edge of the output clock. If this property is set to true, then the > + low jitter mode will affect the falling edge of the output clock. > + type: boolean > + default: false > + > +required: > + - compatible > + - reg > + > +allOf: > + - $ref: rtc.yaml# > + > +additionalProperties: false This should be rather unevaluatedProperties: false > + > +examples: > + - | > + i2c { > + #address-cells = <1>; > + #size-cells = <0>; > + > + rtc@6f { > + compatible = "nxp,pcf85053a"; > + reg = <0x6f>; Please extend the example to include all or almost all properties (which make sense). Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85053a.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf85053a.yaml new file mode 100644 index 000000000000..a1fc29dd30f8 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85053a.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/nxp,pcf85053a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PCF85053A Real Time Clock + +maintainers: + - Carlos Menin <menin@carlosaurelio.net> + +properties: + compatible: + enum: + - nxp,pcf85053a + + reg: + maxItems: 1 + + quartz-load-femtofarads: + description: + The capacitive load of the crystal, expressed in femto Farad (fF). + enum: [6000, 7000, 12500] + default: 12500 + + nxp,quartz-drive-control: + description: + The oscillator is designed to be used with quartz with a series resistance + up to 100 kOhms. This covers the typical range of 32.768 kHz quartz + crystals. A low drive mode is available for low series resistance quartz + (up to 60 kOhms). This reduces the current consumption. For very high + series resistance quartz (up to 500 kOhms), there is a high drive mode. + Current consumption increases substantially in this mode. + enum: [low, normal, high] + default: normal + + nxp,low-jitter-mode: + description: + If set to true, will decrease the CLK output jitter, at the cost of + increasing the current consumption. + type: boolean + default: false + + nxp,clk-inverted: + description: + Invert clock output. Normally, the low jitter mode reduces jitter on the + rising edge of the output clock. If this property is set to true, then the + low jitter mode will affect the falling edge of the output clock. + type: boolean + default: false + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml# + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@6f { + compatible = "nxp,pcf85053a"; + reg = <0x6f>; + }; + };