| Message ID | 20190910143945.9364-1-bruno.thomsen@gmail.com |
|---|---|
| State | Rejected |
| Headers | show |
| Series | rtc: pcf2127: default power management mode | expand |
Hi, On 10/09/2019 16:39:45+0200, Bruno Thomsen wrote: > diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c > index 02b069caffd5..694ec8eefea5 100644 > --- a/drivers/rtc/rtc-pcf2127.c > +++ b/drivers/rtc/rtc-pcf2127.c > @@ -37,6 +37,9 @@ > #define PCF2127_BIT_CTRL3_BLF BIT(2) > #define PCF2127_BIT_CTRL3_BF BIT(3) > #define PCF2127_BIT_CTRL3_BTSE BIT(4) > +#define PCF2127_BIT_CTRL3_PWRMNG0 BIT(5) > +#define PCF2127_BIT_CTRL3_PWRMNG1 BIT(6) > +#define PCF2127_BIT_CTRL3_PWRMNG2 BIT(7) > /* Time and date registers */ > #define PCF2127_REG_SC 0x03 > #define PCF2127_BIT_SC_OSF BIT(7) > @@ -484,10 +487,22 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, > /* > * Disable battery low/switch-over timestamp and interrupts. > * Clear battery interrupt flags which can block new trigger events. > + * Power management configuration: > + * - Battery switch-over function is operating in standard mode. > + * Hardware has to ensure VDD drops slower than 0.7 V/ms otherwise > + * oscillator stop can occur. Since switch-over threshold is typical > + * 2.5 V and sampled every 1 ms with a power management operating > + * limit of 1.8 V. See NXP AN11186 for more info. > + * - Battery low detection function is enabled. > + * - Extra power fail detection function is enabled. > + * > * Note: This is the default chip behaviour but added to ensure > * correct tamper timestamp and interrupt function. > */ > ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, > + PCF2127_BIT_CTRL3_PWRMNG2 | > + PCF2127_BIT_CTRL3_PWRMNG1 | > + PCF2127_BIT_CTRL3_PWRMNG0 | I'm sorry for the late reply but you can't do that specifically because setting those bits maybe be intentional and that would break existing users.
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 02b069caffd5..694ec8eefea5 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -37,6 +37,9 @@ #define PCF2127_BIT_CTRL3_BLF BIT(2) #define PCF2127_BIT_CTRL3_BF BIT(3) #define PCF2127_BIT_CTRL3_BTSE BIT(4) +#define PCF2127_BIT_CTRL3_PWRMNG0 BIT(5) +#define PCF2127_BIT_CTRL3_PWRMNG1 BIT(6) +#define PCF2127_BIT_CTRL3_PWRMNG2 BIT(7) /* Time and date registers */ #define PCF2127_REG_SC 0x03 #define PCF2127_BIT_SC_OSF BIT(7) @@ -484,10 +487,22 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, /* * Disable battery low/switch-over timestamp and interrupts. * Clear battery interrupt flags which can block new trigger events. + * Power management configuration: + * - Battery switch-over function is operating in standard mode. + * Hardware has to ensure VDD drops slower than 0.7 V/ms otherwise + * oscillator stop can occur. Since switch-over threshold is typical + * 2.5 V and sampled every 1 ms with a power management operating + * limit of 1.8 V. See NXP AN11186 for more info. + * - Battery low detection function is enabled. + * - Extra power fail detection function is enabled. + * * Note: This is the default chip behaviour but added to ensure * correct tamper timestamp and interrupt function. */ ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, + PCF2127_BIT_CTRL3_PWRMNG2 | + PCF2127_BIT_CTRL3_PWRMNG1 | + PCF2127_BIT_CTRL3_PWRMNG0 | PCF2127_BIT_CTRL3_BTSE | PCF2127_BIT_CTRL3_BF | PCF2127_BIT_CTRL3_BIE |
This improves the rtc driver robustness by ensuring that the chip power management functions are operating in default mode. As out-of-tree drivers could have changed mode thus resulting in subtle differences that isn't immediately revealed on upgraded System-on-Modules (SoM). This happens since chip configuration is unchanged during reboot and power-cycle of the SoM. Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> --- drivers/rtc/rtc-pcf2127.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)