From patchwork Wed May 20 08:26:20 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 27452 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-gx0-f183.google.com (mail-gx0-f183.google.com [209.85.217.183]) by bilbo.ozlabs.org (Postfix) with ESMTP id 6BCC7B7067 for ; Wed, 20 May 2009 18:26:40 +1000 (EST) Received: by gxk3 with SMTP id 3so112338gxk.17 for ; Wed, 20 May 2009 01:26:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=beta; h=domainkey-signature:received:received:x-sender:x-apparently-to :received:received:received-spf:authentication-results:received :x-virus-scanned:received:received:date:from:to:subject:message-id :references:mime-version:content-type:in-reply-to:user-agent :reply-to:sender:precedence:x-google-loop:mailing-list:list-id :list-post:list-help:list-unsubscribe:x-beenthere-env:x-beenthere; bh=Sk2/FA7/mjMNr9XPMWdoaHR4KGzqbKVvWMgccdA3/ew=; b=jSUulWSUqJooqczQCg9EgGmnbMUsWB9Nfn2DR2w6tOpZBi3kGl7s+eAwE4WPi4x4vC Wiqeof1oPwzPiU3JQMwZtCMvHbCUkC92kCMhHWkLIAaVudWVLUwTj9ifvV1GX1wQEUa9 qRxiCvUdBu877rMFG9UtVzdLUeGLyTs4gF+fY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlegroups.com; s=beta; h=x-sender:x-apparently-to:received-spf:authentication-results :x-virus-scanned:date:from:to:subject:message-id:references :mime-version:content-type:in-reply-to:user-agent:reply-to:sender :precedence:x-google-loop:mailing-list:list-id:list-post:list-help :list-unsubscribe:x-beenthere-env:x-beenthere; b=CmvJ2Cn1YHMhAdkdpTBXVQWTk1izALMMDLZPT8eqh+4gtxOUJCSahsZikorVnHcrtU Jv9BnBGqPBlvepR6R2fIm+/Ilzwlgxv4mXaz8nDzH/HAxKlNTDpWcnBh/IT7jd/YYsRS rSAmnJF3kkYGgGr2EFWwho0H8rUSm91Didy+Y= Received: by 10.100.106.12 with SMTP id e12mr87627anc.28.1242807994602; Wed, 20 May 2009 01:26:34 -0700 (PDT) Received: by 10.106.241.10 with SMTP id o10gr2388prh.0; Wed, 20 May 2009 01:26:34 -0700 (PDT) X-Sender: daniel@caiaq.de X-Apparently-To: rtc-linux@googlegroups.com Received: by 10.223.113.201 with SMTP id b9mr12623faq.26.1242807992724; Wed, 20 May 2009 01:26:32 -0700 (PDT) Received: from buzzloop.caiaq.de (buzzloop.caiaq.de [212.112.241.133]) by gmr-mx.google.com with ESMTP id d8si32323fga.15.2009.05.20.01.26.32; Wed, 20 May 2009 01:26:32 -0700 (PDT) Received-SPF: pass (google.com: domain of daniel@caiaq.de designates 212.112.241.133 as permitted sender) client-ip=212.112.241.133; Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of daniel@caiaq.de designates 212.112.241.133 as permitted sender) smtp.mail=daniel@caiaq.de Received: from localhost (localhost [127.0.0.1]) by buzzloop.caiaq.de (Postfix) with ESMTP id 95B577C801A; Wed, 20 May 2009 10:26:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at buzzloop.caiaq.de Received: from buzzloop.caiaq.de ([127.0.0.1]) by localhost (buzzloop.caiaq.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DbuIaunJIZye; Wed, 20 May 2009 10:26:21 +0200 (CEST) Received: by buzzloop.caiaq.de (Postfix, from userid 1000) id ABAE07C8003; Wed, 20 May 2009 10:26:20 +0200 (CEST) Date: Wed, 20 May 2009 10:26:20 +0200 From: Daniel Mack To: linux-arm-kernel@lists.arm.linux.org.uk, rtc-linux@googlegroups.com, Alessandro Zummo Subject: [rtc-linux] Re: [PATCH 2/3] ARM: MXC: add driver for MXC's internal RTC module Message-ID: <20090520082620.GA3651@buzzloop.caiaq.de> References: <1242737488-11183-1-git-send-email-daniel@caiaq.de> <1242737488-11183-2-git-send-email-daniel@caiaq.de> <20090519144607.GL25674@buzzloop.caiaq.de> <20090519204030.GN9288@pengutronix.de> Mime-Version: 1.0 In-Reply-To: <20090519204030.GN9288@pengutronix.de> User-Agent: Mutt/1.5.18 (2008-05-17) Reply-To: rtc-linux@googlegroups.com Sender: rtc-linux@googlegroups.com Precedence: bulk X-Google-Loop: groups Mailing-List: list rtc-linux@googlegroups.com; contact rtc-linux+owner@googlegroups.com List-Id: List-Post: List-Help: List-Unsubscribe: , X-BeenThere-Env: rtc-linux@googlegroups.com X-BeenThere: rtc-linux@googlegroups.com Hi Sascha, On Tue, May 19, 2009 at 10:40:30PM +0200, Sascha Hauer wrote: > Comments inline, many thanks for your review. I addressed all of your comments, and the last ones from Alessandro. New patch attached. Daniel From 35a1949e752aa782d7d8e0b0e7ee69b3d37649c7 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 18 May 2009 21:41:44 +0200 Subject: [PATCH v3] ARM: MXC: add driver for MXC's internal RTC module This adds a driver for Freescale's MXC internal real time clock modules. The code is taken from Freescale's BSPs, but modified to fit the current kernel coding mechanisms. Also, the PMIC external clock function was removed for now to not add dead bits and keep the code as simple as possible. Signed-off-by: Daniel Mack Cc: Sascha Hauer Cc: Alessandro Zummo --- drivers/rtc/Kconfig | 11 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-mxc.c | 555 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 567 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/rtc-mxc.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 4e9851f..7f2a663 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -491,6 +491,17 @@ config RTC_DRV_M48T59 This driver can also be built as a module, if so, the module will be called "rtc-m48t59". +config RTC_MXC + tristate "Freescale MXC Real Time Clock" + depends on ARCH_MXC + depends on RTC_CLASS + help + If you say yes here you get support for the Freescale MXC + RTC module. + + This driver can also be built as a module, if so, the module + will be called "rtc-mxc". + config RTC_DRV_BQ4802 tristate "TI BQ4802" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6c0639a..018a908 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o +obj-$(CONFIG_RTC_MXC) += rtc-mxc.o obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o diff --git a/drivers/rtc/rtc-mxc.c b/drivers/rtc/rtc-mxc.c new file mode 100644 index 0000000..1dc7c61 --- /dev/null +++ b/drivers/rtc/rtc-mxc.c @@ -0,0 +1,555 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define RTC_INPUT_CLK_32768HZ (0x00 << 5) +#define RTC_INPUT_CLK_32000HZ (0x01 << 5) +#define RTC_INPUT_CLK_38400HZ (0x02 << 5) + +#define RTC_SW_BIT (1 << 0) +#define RTC_ALM_BIT (1 << 2) +#define RTC_1HZ_BIT (1 << 4) +#define RTC_2HZ_BIT (1 << 7) +#define RTC_SAM0_BIT (1 << 8) +#define RTC_SAM1_BIT (1 << 9) +#define RTC_SAM2_BIT (1 << 10) +#define RTC_SAM3_BIT (1 << 11) +#define RTC_SAM4_BIT (1 << 12) +#define RTC_SAM5_BIT (1 << 13) +#define RTC_SAM6_BIT (1 << 14) +#define RTC_SAM7_BIT (1 << 15) +#define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ + RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ + RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) + +#define RTC_ENABLE_BIT (1 << 7) + +#define MAX_PIE_NUM 9 +#define MAX_PIE_FREQ 512 +const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { + { 2, RTC_2HZ_BIT }, + { 4, RTC_SAM0_BIT }, + { 8, RTC_SAM1_BIT }, + { 16, RTC_SAM2_BIT }, + { 32, RTC_SAM3_BIT }, + { 64, RTC_SAM4_BIT }, + { 128, RTC_SAM5_BIT }, + { 256, RTC_SAM6_BIT }, + { MAX_PIE_FREQ, RTC_SAM7_BIT }, +}; + +/* Those are the bits from a classic RTC we want to mimic */ +#define RTC_IRQF 0x80 /* any of the following 3 is active */ +#define RTC_PF 0x40 /* Periodic interrupt */ +#define RTC_AF 0x20 /* Alarm interrupt */ +#define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ + +#define MXC_RTC_TIME 0 +#define MXC_RTC_ALARM 1 + +#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ +#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ +#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ +#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ +#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ +#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ +#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ +#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ +#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ +#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ +#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ +#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ +#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ + +struct rtc_plat_data { + struct rtc_device *rtc; + void __iomem *ioaddr; + int irq; + struct clk *clk; + unsigned int irqen; + int alrm_sec; + int alrm_min; + int alrm_hour; + int alrm_mday; + struct timespec mxc_rtc_delta; +}; + +static u32 rtc_freq = 2; /* minimum value for PIE */ + +static struct rtc_time g_rtc_alarm; + +/* + * This function is used to obtain the RTC time or the alarm value in + * second. + */ +static u32 get_alarm_or_time(struct device *dev, int time_alarm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; + + switch (time_alarm) { + case MXC_RTC_TIME: + day = readw(ioaddr + RTC_DAYR); + hr_min = readw(ioaddr + RTC_HOURMIN); + sec = readw(ioaddr + RTC_SECOND); + break; + case MXC_RTC_ALARM: + day = readw(ioaddr + RTC_DAYALARM); + hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; + sec = readw(ioaddr + RTC_ALRM_SEC); + break; + } + + hr = hr_min >> 8; + min = hr_min & 0xff; + + return (((day * 24 + hr) * 60) + min) * 60 + sec; +} + +/* + * This function sets the RTC alarm value or the time value. + */ +static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) +{ + u32 day, hr, min, sec, temp; + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + day = time / 86400; + time -= day * 86400; + + /* time is within a day now */ + hr = time / 3600; + time -= hr * 3600; + + /* time is within an hour now */ + min = time / 60; + sec = time - min * 60; + + temp = (hr << 8) + min; + + switch (time_alarm) { + case MXC_RTC_TIME: + writew(day, ioaddr + RTC_DAYR); + writew(sec, ioaddr + RTC_SECOND); + writew(temp, ioaddr + RTC_HOURMIN); + break; + case MXC_RTC_ALARM: + writew(day, ioaddr + RTC_DAYALARM); + writew(sec, ioaddr + RTC_ALRM_SEC); + writew(temp, ioaddr + RTC_ALRM_HM); + break; + } +} + +/* + * This function updates the RTC alarm registers and then clears all the + * interrupt status bits. + */ +static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) +{ + struct rtc_time alarm_tm, now_tm; + unsigned long now, time; + int ret; + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + now = get_alarm_or_time(dev, MXC_RTC_TIME); + rtc_time_to_tm(now, &now_tm); + alarm_tm.tm_year = now_tm.tm_year; + alarm_tm.tm_mon = now_tm.tm_mon; + alarm_tm.tm_mday = now_tm.tm_mday; + alarm_tm.tm_hour = alrm->tm_hour; + alarm_tm.tm_min = alrm->tm_min; + alarm_tm.tm_sec = alrm->tm_sec; + rtc_tm_to_time(&now_tm, &now); + rtc_tm_to_time(&alarm_tm, &time); + + if (time < now) { + time += 60 * 60 * 24; + rtc_time_to_tm(time, &alarm_tm); + } + + ret = rtc_tm_to_time(&alarm_tm, &time); + + /* clear all the interrupt status bits */ + writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); + set_alarm_or_time(dev, MXC_RTC_ALARM, time); + + return ret; +} + +/* This function is the RTC interrupt service routine. */ +static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) +{ + struct platform_device *pdev = dev_id; + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 status; + u32 events = 0; + + spin_lock_irq(&pdata->rtc->irq_lock); + status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); + /* clear interrupt sources */ + writew(status, ioaddr + RTC_RTCISR); + + /* clear alarm interrupt if it has occurred */ + if (status & RTC_ALM_BIT) + status &= ~RTC_ALM_BIT; + + /* update irq data & counter */ + if (status & RTC_ALM_BIT) + events |= (RTC_AF | RTC_IRQF); + + if (status & RTC_1HZ_BIT) + events |= (RTC_UF | RTC_IRQF); + + if (status & PIT_ALL_ON) + events |= (RTC_PF | RTC_IRQF); + + if ((status & RTC_ALM_BIT) && rtc_valid_tm(&g_rtc_alarm)) + rtc_update_alarm(&pdev->dev, &g_rtc_alarm); + + rtc_update_irq(pdata->rtc, 1, events); + spin_unlock_irq(&pdata->rtc->irq_lock); + + return IRQ_HANDLED; +} + +static int mxc_rtc_open(struct device *dev) +{ + return 0; +} + +/* + * Clear all interrupts and release the IRQ + */ +static void mxc_rtc_release(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + spin_lock_irq(&pdata->rtc->irq_lock); + + /* Disable all rtc interrupts */ + writew(0, ioaddr + RTC_RTCIENR); + + /* Clear all interrupt status */ + writew(0xffffffff, ioaddr + RTC_RTCISR); + + spin_unlock_irq(&pdata->rtc->irq_lock); +} + +static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, + unsigned int enabled) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + u32 reg; + + spin_lock_irq(&pdata->rtc->irq_lock); + reg = readw(ioaddr + RTC_RTCIENR); + + if (enabled) + reg |= bit; + else + reg &= ~bit; + + writew(reg, ioaddr + RTC_RTCIENR); + spin_unlock_irq(&pdata->rtc->irq_lock); +} + +/* + * This function is used to support some ioctl calls directly. + */ +static int mxc_rtc_ioctl(struct device *dev, unsigned int cmd, + unsigned long arg) +{ + int i; + + switch (cmd) { + case RTC_IRQP_SET: + if (arg < 2 || arg > MAX_PIE_FREQ || (arg % 2) != 0) + return -EINVAL; /* Also make sure a power of 2Hz */ + if ((arg > 64) && (!capable(CAP_SYS_RESOURCE))) + return -EACCES; + rtc_freq = arg; + return 0; + + case RTC_IRQP_READ: + return put_user(rtc_freq, (u32 *) arg); + + case RTC_PIE_ON: + for (i = 0; i < MAX_PIE_NUM; i++) + if (PIE_BIT_DEF[i][0] == rtc_freq) + break; + + if (i == MAX_PIE_NUM) + return -EACCES; + + mxc_rtc_irq_enable(dev, PIE_BIT_DEF[i][1], 1); + return 0; + + case RTC_PIE_OFF: + mxc_rtc_irq_enable(dev, PIT_ALL_ON, 0); + return 0; + } + + return -ENOIOCTLCMD; +} + +static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); + return 0; +} + +static int mxc_rtc_update_irq_enable(struct device *dev, unsigned int enabled) +{ + mxc_rtc_irq_enable(dev, RTC_1HZ_BIT, enabled); + return 0; +} + +/* + * This function reads the current RTC time into tm in Gregorian date. + */ +static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + u32 val; + + /* Avoid roll-over from reading the different registers */ + do { + val = get_alarm_or_time(dev, MXC_RTC_TIME); + } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); + + rtc_time_to_tm(val, tm); + + return 0; +} + +/* + * This function sets the internal RTC time based on tm in Gregorian date. + */ +static int mxc_rtc_set_mmss(struct device *dev, unsigned long time) +{ + /* Avoid roll-over from reading the different registers */ + do { + set_alarm_or_time(dev, MXC_RTC_TIME, time); + } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); + + return 0; +} + +/* + * This function reads the current alarm value into the passed in 'alrm' + * argument. It updates the alrm's pending field value based on the whether + * an alarm interrupt occurs or not. + */ +static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + void __iomem *ioaddr = pdata->ioaddr; + + rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); + alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; + + return 0; +} + +/* + * This function sets the RTC alarm based on passed in alrm. + */ +static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + int ret; + + if (rtc_valid_tm(&alrm->time)) { + if (alrm->time.tm_sec > 59 || + alrm->time.tm_hour > 23 || + alrm->time.tm_min > 59) + return -EINVAL; + + ret = rtc_update_alarm(dev, &alrm->time); + } else { + ret = rtc_valid_tm(&alrm->time); + if (ret) + return ret; + + ret = rtc_update_alarm(dev, &alrm->time); + } + + if (ret) + return ret; + + memcpy(&g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); + mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); + + return 0; +} + +/* RTC layer */ +static struct rtc_class_ops mxc_rtc_ops = { + .open = mxc_rtc_open, + .release = mxc_rtc_release, + .ioctl = mxc_rtc_ioctl, + .read_time = mxc_rtc_read_time, + .set_mmss = mxc_rtc_set_mmss, + .read_alarm = mxc_rtc_read_alarm, + .set_alarm = mxc_rtc_set_alarm, + .alarm_irq_enable = mxc_rtc_alarm_irq_enable, + .update_irq_enable = mxc_rtc_update_irq_enable, +}; + +static int __init mxc_rtc_probe(struct platform_device *pdev) +{ + struct clk *clk; + struct resource *res; + struct rtc_device *rtc; + struct rtc_plat_data *pdata = NULL; + u32 reg; + int ret, rate; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->ioaddr = ioremap(res->start, resource_size(res)); + + clk = clk_get(&pdev->dev, "ckil"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate = clk_get_rate(clk); + clk_put(clk); + + if (rate == 32768) + reg = RTC_INPUT_CLK_32768HZ; + else if (rate == 32000) + reg = RTC_INPUT_CLK_32000HZ; + else if (rate == 38400) + reg = RTC_INPUT_CLK_38400HZ; + else { + dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", + clk_get_rate(clk)); + ret = -EINVAL; + goto exit_free_pdata; + } + + reg |= RTC_ENABLE_BIT; + writew(reg, (pdata->ioaddr + RTC_RTCCTL)); + if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { + dev_err(&pdev->dev, "hardware module can't be enabled!\n"); + ret = -EIO; + goto exit_free_pdata; + } + + pdata->clk = clk_get(&pdev->dev, "rtc"); + if (IS_ERR(pdata->clk)) { + dev_err(&pdev->dev, "unable to get clock!\n"); + ret = PTR_ERR(pdata->clk); + goto exit_free_pdata; + } + + clk_enable(pdata->clk); + + rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops, + THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto exit_put_clk; + } + + pdata->rtc = rtc; + platform_set_drvdata(pdev, pdata); + + /* Configure and enable the RTC */ + pdata->irq = platform_get_irq(pdev, 0); + + if (pdata->irq >= 0) { + if (request_irq(pdata->irq, mxc_rtc_interrupt, IRQF_SHARED, + pdev->name, pdev) < 0) { + dev_warn(&pdev->dev, "interrupt not available.\n"); + pdata->irq = -1; + } + } + + return 0; + +exit_put_clk: + clk_put(pdata->clk); + +exit_free_pdata: + kfree(pdata); + + return ret; +} + +static int __exit mxc_rtc_remove(struct platform_device *pdev) +{ + struct rtc_plat_data *pdata = platform_get_drvdata(pdev); + + rtc_device_unregister(pdata->rtc); + + if (pdata->irq >= 0) + free_irq(pdata->irq, pdev); + + clk_disable(pdata->clk); + clk_put(pdata->clk); + kfree(pdata); + mxc_rtc_release(NULL); + + return 0; +} + +static struct platform_driver mxc_rtc_driver = { + .driver = { + .name = "mxc_rtc", + .owner = THIS_MODULE, + }, + .remove = __exit_p(mxc_rtc_remove), +}; + +static int __init mxc_rtc_init(void) +{ + return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe); +} + +static void __exit mxc_rtc_exit(void) +{ + platform_driver_unregister(&mxc_rtc_driver); +} + +module_init(mxc_rtc_init); +module_exit(mxc_rtc_exit); + +MODULE_AUTHOR("Daniel Mack "); +MODULE_DESCRIPTION("RTC driver for Freescale MXC"); +MODULE_LICENSE("GPL"); +