From patchwork Fri Nov 3 17:32:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Bhat X-Patchwork-Id: 834025 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-rtc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=timesys-com.20150623.gappssmtp.com header.i=@timesys-com.20150623.gappssmtp.com header.b="b9swHsjC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yT8FG1vkHz9sBW for ; Sat, 4 Nov 2017 04:33:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756384AbdKCRdh (ORCPT ); Fri, 3 Nov 2017 13:33:37 -0400 Received: from mail-qt0-f193.google.com ([209.85.216.193]:53947 "EHLO mail-qt0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756217AbdKCRdf (ORCPT ); Fri, 3 Nov 2017 13:33:35 -0400 Received: by mail-qt0-f193.google.com with SMTP id n61so4117573qte.10 for ; Fri, 03 Nov 2017 10:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=timesys-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1UWssTkZ+1wJrarr5J6+x3Ka3ZDIfZU3oaqwgCB5PUQ=; b=b9swHsjC8V43sKYiTUmsDpAWCQjbexVCMkRgM7koJ+6pbmYMDFNwucxnueQCcdqBC2 +9JLwDsnaBvnaoc5P7kTRuXLb0MM6EYF0baxxKs024KWJU4xa19vDNyBeq36Qx3UicqE s8Oz3ZZMufdde7OzCkzwhppOw6lp2KsMmZhtnvaimv4fgnz/w2JmhUVbCUHicLc9OWnz E3BMwmTObSLARQZqwSyfCw456CAlF3gmK14InhwY+8h1S4oW8mBb/EeH6+ieymjcYz/3 +e8kZuPsv/FdwZJ/pBEnkwaAwEddGJZcqTEjuk1fU025xT7kWf+JvioRns+O0dScY/+P Dn9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1UWssTkZ+1wJrarr5J6+x3Ka3ZDIfZU3oaqwgCB5PUQ=; b=hw3xs5FXcWA0m/bJPnQ2sqAQ9MccjD22erSlzZG4VoxpZEkwvreYmDJVLKzKxp7YCv 8g1ycMulHgNTej25y43LMm9mUs4NmD4GT7j98r4p5svlcOYk8srk2emkLyVbqvHJJ0zB 9pwlyfdwYHaU1c2G0o6MtrOo6blpoeYQ4qwbXXDs50cdTVIzrziVs2bdNFfsgEs+XYMB Nx7CD0bcoF9IvnVpHpcWwH9217FsymfDACoxgvKtIDqWcExwGsswGU4m/JnR2XdrW3SH yDSgjSz3qYvtVfaLRzUWDTsK+YI8RpCVmlv4EePFn8VJwWT7CzkUQTsxNK7sAkU5Scq+ ZLcg== X-Gm-Message-State: AJaThX47ZF70fUCLLWjTJHUvEMFRT5AAif7PXRSZuBmN+T2lmrFNmClD GbvGLp9EHIH7jxJJBQSfPs9Mjjw+ X-Google-Smtp-Source: ABhQp+ShXDCZmI838tIXnjYhn4ptq0VVAkU0q3UGaSjt/+9HqgSdE5lHU1uv2nGVRLLvZDlLUhlk+A== X-Received: by 10.200.27.221 with SMTP id m29mr660682qtk.152.1509730414834; Fri, 03 Nov 2017 10:33:34 -0700 (PDT) Received: from timesysax.timesys.com (96-94-100-129-static.hfc.comcastbusiness.net. [96.94.100.129]) by smtp.gmail.com with ESMTPSA id n131sm4161188qke.48.2017.11.03.10.33.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:33:34 -0700 (PDT) From: Akshay Bhat To: a.zummo@towertech.it, alexandre.belloni@free-electrons.com Cc: linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org, Akshay Bhat Subject: [PATCH 2/3] rtc: rx8010: Specify correct address for RX8010_RESV31 Date: Fri, 3 Nov 2017 13:32:40 -0400 Message-Id: <1509730361-23905-2-git-send-email-akshay.bhat@timesys.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509730361-23905-1-git-send-email-akshay.bhat@timesys.com> References: <1509730361-23905-1-git-send-email-akshay.bhat@timesys.com> Sender: linux-rtc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rtc@vger.kernel.org Define for reserved register 31 had the incorrect address. Specify the correct address. Reported-by: Jens-Peter Oswald Signed-off-by: Akshay Bhat --- drivers/rtc/rtc-rx8010.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-rx8010.c b/drivers/rtc/rtc-rx8010.c index f948f75..2e06e5f 100644 --- a/drivers/rtc/rtc-rx8010.c +++ b/drivers/rtc/rtc-rx8010.c @@ -35,7 +35,7 @@ #define RX8010_CTRL 0x1F /* 0x20 to 0x2F are user registers */ #define RX8010_RESV30 0x30 -#define RX8010_RESV31 0x32 +#define RX8010_RESV31 0x31 #define RX8010_IRQ 0x32 #define RX8010_EXT_WADA BIT(3)