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[140.112.30.76]) by gmr-mx.google.com with ESMTPS id un17si1624706pab.0.2016.06.15.03.27.56 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Jun 2016 03:27:56 -0700 (PDT) Received-SPF: neutral (google.com: 140.112.30.76 is neither permitted nor denied by best guess record for domain of wens@wens.csie.org) client-ip=140.112.30.76; Received: by wens.csie.org (Postfix, from userid 1000) id BB3F65F9E8; Wed, 15 Jun 2016 18:27:51 +0800 (CST) From: Chen-Yu Tsai To: Mark Brown , Lee Jones , Alessandro Zummo , Alexandre Belloni , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Maxime Ripard , Michael Turquette , Stephen Boyd Cc: Chen-Yu Tsai , rtc-linux@googlegroups.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [rtc-linux] [PATCH v2 10/10] ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for osc32k Date: Wed, 15 Jun 2016 18:27:47 +0800 Message-Id: <1465986467-14802-11-git-send-email-wens@csie.org> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1465986467-14802-1-git-send-email-wens@csie.org> References: <1465986467-14802-1-git-send-email-wens@csie.org> X-Original-Sender: wens@csie.org X-Original-Authentication-Results: gmr-mx.google.com; spf=neutral (google.com: 140.112.30.76 is neither permitted nor denied by best guess record for domain of wens@wens.csie.org) smtp.mailfrom=wens@wens.csie.org Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Spam-Checked-In-Group: rtc-linux@googlegroups.com X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , The 32.768 kHz clock inside the A80 SoC is fed from an external source, typically the AC100 RTC module. Make the osc32k placeholder a fixed-factor clock so board dts files can specify its source. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80-optimus.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80.dtsi | 9 +++------ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 65f4f32f89ad..b6299a9c14e3 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -103,6 +103,11 @@ allwinner,drive = ; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_cubieboard4: led-pins@0 { allwinner,pins = "PH6", "PH17"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 3b013dc5fef1..2f079cbd2025 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -152,6 +152,11 @@ status = "okay"; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f68b3242b33a..dd11115ec087 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -148,15 +148,12 @@ /* * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This clock is by default enabled - * and clocked at 32768 Hz, from the oscillator connected - * to the AC100. It is configurable, but no such driver or - * bindings exist yet. + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. */ osc32k: osc32k_clk { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "fixed-factor-clock"; clock-output-names = "osc32k"; };