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[216.228.121.64]) by gmr-mx.google.com with ESMTPS id tn7si1489580pac.1.2016.01.28.05.49.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jan 2016 05:49:23 -0800 (PST) Received-SPF: pass (google.com: domain of ldewangan@nvidia.com designates 216.228.121.64 as permitted sender) client-ip=216.228.121.64; Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 28 Jan 2016 05:49:29 -0800 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 28 Jan 2016 05:50:15 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 28 Jan 2016 05:50:15 -0800 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.406.0; Thu, 28 Jan 2016 05:49:21 -0800 From: Laxman Dewangan To: , , , , , , , , , , CC: , , , , , , , , Laxman Dewangan Subject: [rtc-linux] [PATCH V6 3/8] DT: pinctrl: add DT binding doc for pincontrol of PMIC max77620/max20024 Date: Thu, 28 Jan 2016 19:07:49 +0530 Message-ID: <1453988274-28052-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453988274-28052-1-git-send-email-ldewangan@nvidia.com> References: <1453988274-28052-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-Original-Sender: ldewangan@nvidia.com X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of ldewangan@nvidia.com designates 216.228.121.64 as permitted sender) smtp.mailfrom=ldewangan@nvidia.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Spam-Checked-In-Group: rtc-linux@googlegroups.com X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins which act as GPIO as well as special function mode. Add DT binding document to configure pins in function mode as well as pin configuration parameters. Signed-off-by: Laxman Dewangan Acked-by: Rob Herring --- Changes from V4: - Separate out from pincontrol driver .../bindings/pinctrl/pinctrl-max77620.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt new file mode 100644 index 0000000..6536786 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt @@ -0,0 +1,87 @@ +Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor. + +Device has 8 GPIO pins which can be configured as GPIO as well as the +special IO functions. + +Please refer file +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are require if pin control setting is required at boot. +- pinctrl-names: A pinctrl state named per . +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + . + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +- pins: List of pins. Valid values of pins properties are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7. + +Optional properties: +Following are optional properties defined as pinmux DT binding document +. Absence of properties will leave the configuration +on default. + function, + drive-push-pull, + drive-open-drain, + bias-pull-up, + bias-pull-down. + +Valid values for function properties are: + gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, + reference-out + +Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. +The properties are required to configure these resource FPS parameters +when system is in "active" state or in "suspend" state. +Here "active" state means system is UP and working normally. +"suspend" state means system enters into the suspend state. + +- maxim,active-fps-source: FPS source for the gpios in active state + of the GPIO. Valid values are FPS_SRC_0, + FPS_SRC_1, FPS_SRC_2 and FPS_SRC_NONE. + Absence of this property will leave the pin + on default. +- maxim,active-fps-power-up-slot: Power up slot on given FPS for active state. + Valid values are 0 to 7. +- maxim,active-fps-power-down-slot: Power down slot on given FPS for active + state. Valid values are 0 to 7. +- maxim,suspend-fps-source: Suspend state FPS source. Valid values are + same as maxim,active-fps-source. +- maxim,suspend-fps-power-down-slot: Suspend state power down slot. Valid + values are 0 to 7. +- maxim,suspend-fps-power-up-slot: Suspend state power up slot. Valid values + are 0 to 7. + +Example: +-------- +#include +... +max77620@3c { + + pinctrl-names = "default"; + pinctrl-0 = <&spmic_default>; + + spmic_default: pinmux@0 { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,fps-source = ; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,fps-source = ; + }; + }; +};