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riscv: Call set_satp_mode_max_supported in riscv_host_cpu_init

Message ID mvm34zavbmb.fsf@suse.de
State New
Headers show
Series riscv: Call set_satp_mode_max_supported in riscv_host_cpu_init | expand

Commit Message

Andreas Schwab Sept. 19, 2023, 7:57 a.m. UTC 
When running in KVM mode with -cpu host, cfg.satp_mode.supported is not
initialized, causing an infinite loop in riscv_cpu_satp_mode_finalize.

Fixes: 6df3747a27 ("riscv: Introduce satp mode hw capabilities")
Signed-off-by: Andreas Schwab <schwab@suse.de>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Andrew Jones Sept. 19, 2023, 11:18 a.m. UTC | #1 
On Tue, Sep 19, 2023 at 09:57:32AM +0200, Andreas Schwab wrote:
> When running in KVM mode with -cpu host, cfg.satp_mode.supported is not
> initialized, causing an infinite loop in riscv_cpu_satp_mode_finalize.
> 
> Fixes: 6df3747a27 ("riscv: Introduce satp mode hw capabilities")
> Signed-off-by: Andreas Schwab <schwab@suse.de>
> ---
>  target/riscv/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f227c7664e..bb8dc3bb40 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -623,8 +623,10 @@ static void riscv_host_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>  #if defined(TARGET_RISCV32)
>      set_misa(env, MXL_RV32, 0);
> +    set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
>  #elif defined(TARGET_RISCV64)
>      set_misa(env, MXL_RV64, 0);
> +    set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
>  #endif
>      riscv_cpu_add_user_properties(obj);
>  }
> -- 
> 2.42.0
>

This should be fixed by

https://lore.kernel.org/all/20230911064320.939791-37-alistair.francis@wdc.com/

Thanks,
drew
Andreas Schwab Sept. 20, 2023, 1:31 p.m. UTC | #2 
On Sep 19 2023, Andrew Jones wrote:

> This should be fixed by
>
> https://lore.kernel.org/all/20230911064320.939791-37-alistair.francis@wdc.com/

Thanks, I can confirm that it fixes the issue.
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f227c7664e..bb8dc3bb40 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -623,8 +623,10 @@  static void riscv_host_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
 #if defined(TARGET_RISCV32)
     set_misa(env, MXL_RV32, 0);
+    set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
 #elif defined(TARGET_RISCV64)
     set_misa(env, MXL_RV64, 0);
+    set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
 #endif
     riscv_cpu_add_user_properties(obj);
 }