From patchwork Fri May 25 11:29:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 161304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 58071B6F77 for ; Fri, 25 May 2012 21:29:05 +1000 (EST) Received: from localhost ([::1]:39439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SXsha-0004Mh-FR for incoming@patchwork.ozlabs.org; Fri, 25 May 2012 07:29:02 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40943) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SXsc0-0006Yo-Ms for qemu-devel@nongnu.org; Fri, 25 May 2012 07:23:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SXsbv-0007Zb-Qe for qemu-devel@nongnu.org; Fri, 25 May 2012 07:23:16 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:46131) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SXsbu-0007ZH-U2 for qemu-devel@nongnu.org; Fri, 25 May 2012 07:23:11 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q4PBt6Wk031608; Fri, 25 May 2012 19:55:06 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 496371460599; Fri, 25 May 2012 19:29:16 +0800 (CST) From: Guan Xuetao To: qemu-devel@nongnu.org Date: Fri, 25 May 2012 19:29:04 +0800 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, Guan Xuetao Subject: [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds generic cpu state save/load functions for UniCore32 ISA. All architecture related registers are saved or loaded, and no optimization. Signed-off-by: Guan Xuetao --- target-unicore32/machine.c | 99 ++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 99 insertions(+), 0 deletions(-) create mode 100644 target-unicore32/machine.c diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c new file mode 100644 index 0000000..e8c52cd --- /dev/null +++ b/target-unicore32/machine.c @@ -0,0 +1,99 @@ +/* + * Generic machine functions for UniCore32 ISA + * + * Copyright (C) 2010-2012 Guan Xuetao + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation, or any later version. + * See the COPYING file in the top-level directory. + */ +#include "hw/hw.h" + +void cpu_save(QEMUFile *f, void *opaque) +{ + int i; + CPUUniCore32State *env = (CPUUniCore32State *)opaque; + + for (i = 0; i < 32; i++) { + qemu_put_be32(f, env->regs[i]); + } + qemu_put_be32(f, cpu_asr_read(env)); + qemu_put_be32(f, env->bsr); + for (i = 0; i < 6; i++) { + qemu_put_be32(f, env->banked_bsr[i]); + qemu_put_be32(f, env->banked_r29[i]); + qemu_put_be32(f, env->banked_r30[i]); + } + + qemu_put_be32(f, env->cp0.c0_cpuid); + qemu_put_be32(f, env->cp0.c0_cachetype); + qemu_put_be32(f, env->cp0.c1_sys); + qemu_put_be32(f, env->cp0.c2_base); + qemu_put_be32(f, env->cp0.c3_faultstatus); + qemu_put_be32(f, env->cp0.c4_faultaddr); + qemu_put_be32(f, env->cp0.c5_cacheop); + qemu_put_be32(f, env->cp0.c6_tlbop); + + qemu_put_be32(f, env->features); + + if (env->features & UC32_HWCAP_UCF64) { + for (i = 0; i < 16; i++) { + CPU_DoubleU u; + u.d = env->ucf64.regs[i]; + qemu_put_be32(f, u.l.upper); + qemu_put_be32(f, u.l.lower); + } + for (i = 0; i < 32; i++) { + qemu_put_be32(f, env->ucf64.xregs[i]); + } + } +} + +int cpu_load(QEMUFile *f, void *opaque, int version_id) +{ + CPUUniCore32State *env = (CPUUniCore32State *)opaque; + int i; + uint32_t val; + + if (version_id != CPU_SAVE_VERSION) { + return -EINVAL; + } + + for (i = 0; i < 32; i++) { + env->regs[i] = qemu_get_be32(f); + } + val = qemu_get_be32(f); + /* Avoid mode switch when restoring ASR. */ + env->uncached_asr = val & ASR_M; + cpu_asr_write(env, val, 0xffffffff); + env->bsr = qemu_get_be32(f); + for (i = 0; i < 6; i++) { + env->banked_bsr[i] = qemu_get_be32(f); + env->banked_r29[i] = qemu_get_be32(f); + env->banked_r30[i] = qemu_get_be32(f); + } + + env->cp0.c0_cpuid = qemu_get_be32(f); + env->cp0.c0_cachetype = qemu_get_be32(f); + env->cp0.c1_sys = qemu_get_be32(f); + env->cp0.c2_base = qemu_get_be32(f); + env->cp0.c3_faultstatus = qemu_get_be32(f); + env->cp0.c4_faultaddr = qemu_get_be32(f); + env->cp0.c5_cacheop = qemu_get_be32(f); + env->cp0.c6_tlbop = qemu_get_be32(f); + + if (env->features & UC32_HWCAP_UCF64) { + for (i = 0; i < 16; i++) { + CPU_DoubleU u; + u.l.upper = qemu_get_be32(f); + u.l.lower = qemu_get_be32(f); + env->ucf64.regs[i] = u.d; + } + for (i = 0; i < 16; i++) { + env->ucf64.xregs[i] = qemu_get_be32(f); + } + } + + return 0; +}