From patchwork Mon Aug 31 22:09:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 512610 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CD87C1401E7 for ; Tue, 1 Sep 2015 08:13:00 +1000 (AEST) Received: from localhost ([::1]:41484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWXJz-0007tA-1h for incoming@patchwork.ozlabs.org; Mon, 31 Aug 2015 18:12:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWXGb-0002bK-Lb for qemu-devel@nongnu.org; Mon, 31 Aug 2015 18:09:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZWXGY-0006k3-Ez for qemu-devel@nongnu.org; Mon, 31 Aug 2015 18:09:29 -0400 Received: from zose-mta03.web4all.fr ([185.49.20.44]:54093) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZWXGY-0006jy-6G for qemu-devel@nongnu.org; Mon, 31 Aug 2015 18:09:26 -0400 Received: from localhost (localhost [127.0.0.1]) by zose-mta03.web4all.fr (Postfix) with ESMTP id B95B343FBE for ; Tue, 1 Sep 2015 00:09:25 +0200 (CEST) Received: from zose-mta03.web4all.fr ([127.0.0.1]) by localhost (zose-mta03.web4all.fr [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 82UyNE2FV1VJ; Tue, 1 Sep 2015 00:09:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta03.web4all.fr (Postfix) with ESMTP id 4EBAA44055; Tue, 1 Sep 2015 00:09:25 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose-mta-03.w4a.fr Received: from zose-mta03.web4all.fr ([127.0.0.1]) by localhost (zose-mta03.web4all.fr [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 7tMD1JZBGHOf; Tue, 1 Sep 2015 00:09:25 +0200 (CEST) Received: from localhost.localdomain (smm49-1-78-235-240-156.fbx.proxad.net [78.235.240.156]) by zose-mta03.web4all.fr (Postfix) with ESMTPSA id 155F343FBE; Tue, 1 Sep 2015 00:09:25 +0200 (CEST) From: Jean-Christophe Dubois To: qemu-devel@nongnu.org Date: Tue, 1 Sep 2015 00:09:24 +0200 Message-Id: X-Mailer: git-send-email 2.1.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 185.49.20.44 Cc: Jean-Christophe Dubois Subject: [Qemu-devel] [PATCH v15 8/8] i.MX: Add i2C devices to i.MX31 SOC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Crosthwaite --- Changes since v1: * not present on v1 Changes since v2: * not present on v2 Changes since v3: * not present on v3 Changes since v4: * not present on v4 Changes since v5: * not present on v5 Changes since v6: * not present on v6 Changes since v7: * not present on v7 Changes since v8: * not present on v8 Changes since v9: * Added 3 I2C devices to i.MX31 SOC Changes since v10: * no change. Changes since v11: * no change. Changes since v12: * no change. Changes since v13: * Spelling fix in comments * Space cleanup * Patch title fix. Changes since v14: * no change. hw/arm/fsl-imx31.c | 30 ++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx31.h | 11 +++++++++++ 2 files changed, 41 insertions(+) diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 1681ecf..87548c8 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -50,6 +50,11 @@ static void fsl_imx31_init(Object *obj) object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); } + + for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { + object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); + qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); + } } static void fsl_imx31_realize(DeviceState *dev, Error **errp) @@ -154,6 +159,31 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) epit_table[i].irq)); } + /* Initialize all I2C */ + for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } i2c_table[FSL_IMX31_NUM_I2CS] = { + { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, + { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, + { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } + }; + + /* Initialize the I2C */ + object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + /* Map I2C memory */ + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); + /* Connect I2C IRQ to PIC */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, + qdev_get_gpio_in(DEVICE(&s->avic), + i2c_table[i].irq)); + } + /* On a real system, the first 16k is a `secure boot rom' */ memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, "imx31.secure_rom", diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index 128006f..891166f 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -31,6 +31,7 @@ #define FSL_IMX31_NUM_UARTS 2 #define FSL_IMX31_NUM_EPITS 2 +#define FSL_IMX31_NUM_I2CS 3 typedef struct FslIMX31State { /*< private >*/ @@ -43,6 +44,7 @@ typedef struct FslIMX31State { IMXSerialState uart[FSL_IMX31_NUM_UARTS]; IMXGPTState gpt; IMXEPITState epit[FSL_IMX31_NUM_EPITS]; + IMXI2CState i2c[FSL_IMX31_NUM_I2CS]; MemoryRegion secure_rom; MemoryRegion rom; MemoryRegion iram; @@ -57,10 +59,16 @@ typedef struct FslIMX31State { #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000 #define FSL_IMX31_IRAM_SIZE 0x4000 +#define FSL_IMX31_I2C1_ADDR 0x43F80000 +#define FSL_IMX31_I2C1_SIZE 0x4000 +#define FSL_IMX31_I2C3_ADDR 0x43F84000 +#define FSL_IMX31_I2C3_SIZE 0x4000 #define FSL_IMX31_UART1_ADDR 0x43F90000 #define FSL_IMX31_UART1_SIZE 0x4000 #define FSL_IMX31_UART2_ADDR 0x43F94000 #define FSL_IMX31_UART2_SIZE 0x4000 +#define FSL_IMX31_I2C2_ADDR 0x43F98000 +#define FSL_IMX31_I2C2_SIZE 0x4000 #define FSL_IMX31_CCM_ADDR 0x53F80000 #define FSL_IMX31_CCM_SIZE 0x4000 #define FSL_IMX31_GPT_ADDR 0x53F90000 @@ -95,5 +103,8 @@ typedef struct FslIMX31State { #define FSL_IMX31_GPT_IRQ 29 #define FSL_IMX31_UART2_IRQ 32 #define FSL_IMX31_UART1_IRQ 45 +#define FSL_IMX31_I2C1_IRQ 10 +#define FSL_IMX31_I2C2_IRQ 4 +#define FSL_IMX31_I2C3_IRQ 3 #endif /* FSL_IMX31_H */