From patchwork Fri Nov 2 16:08:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fredrik Noring X-Patchwork-Id: 992418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nocrew.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42mnDL6297zB4Vf for ; Sat, 3 Nov 2018 03:13:06 +1100 (AEDT) Received: from localhost ([::1]:52485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIc4G-0004ZH-0o for incoming@patchwork.ozlabs.org; Fri, 02 Nov 2018 12:13:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gIc0S-0000lm-Mf for qemu-devel@nongnu.org; Fri, 02 Nov 2018 12:09:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gIc0N-0003Gn-Q1 for qemu-devel@nongnu.org; Fri, 02 Nov 2018 12:09:08 -0400 Received: from ste-pvt-msa1.bahnhof.se ([213.80.101.70]:13405) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gIc0N-0002uK-AX for qemu-devel@nongnu.org; Fri, 02 Nov 2018 12:09:03 -0400 Received: from localhost (localhost [127.0.0.1]) by ste-pvt-msa1.bahnhof.se (Postfix) with ESMTP id C5CBC40771; Fri, 2 Nov 2018 17:08:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Received: from ste-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (ste-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ps8wO4R2th3f; Fri, 2 Nov 2018 17:08:17 +0100 (CET) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by ste-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id D082C3FE16; Fri, 2 Nov 2018 17:08:17 +0100 (CET) Date: Fri, 2 Nov 2018 17:08:17 +0100 From: Fredrik Noring To: Aleksandar Markovic , Aurelien Jarno , Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 213.80.101.70 Subject: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?J=C3=BCrgen?= Urban , qemu-devel@nongnu.org, "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of the generic gen_HILO. Signed-off-by: Fredrik Noring Reviewed-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 67 ++++++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 11 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 60320cbe69..f3993cf7d7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4359,24 +4359,72 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } +/* Move to and from TX79 HI1/LO1 registers. */ +static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) +{ + if (reg == 0 && (opc == TX79_MMI_MFHI1 || opc == TX79_MMI_MFLO1)) { + /* Treat as NOP. */ + return; + } + + switch (opc) { + case TX79_MMI_MFHI1: +#if defined(TARGET_MIPS64) + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[1]); +#else + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); +#endif + break; + case TX79_MMI_MFLO1: +#if defined(TARGET_MIPS64) + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[1]); +#else + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); +#endif + break; + case TX79_MMI_MTHI1: + if (reg != 0) { +#if defined(TARGET_MIPS64) + tcg_gen_ext32s_tl(cpu_HI[1], cpu_gpr[reg]); +#else + tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); +#endif + } else { + tcg_gen_movi_tl(cpu_HI[1], 0); + } + break; + case TX79_MMI_MTLO1: + if (reg != 0) { +#if defined(TARGET_MIPS64) + tcg_gen_ext32s_tl(cpu_LO[1], cpu_gpr[reg]); +#else + tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); +#endif + } else { + tcg_gen_movi_tl(cpu_LO[1], 0); + } + break; + default: + MIPS_INVAL("MFTHILO TX79"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 || - opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) { + if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { /* Treat as NOP. */ return; } if (acc != 0) { - if (!(ctx->insn_flags & INSN_R5900)) { - check_dsp(ctx); - } + check_dsp(ctx); } switch (opc) { case OPC_MFHI: - case TX79_MMI_MFHI1: #if defined(TARGET_MIPS64) if (acc != 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); @@ -4387,7 +4435,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) } break; case OPC_MFLO: - case TX79_MMI_MFLO1: #if defined(TARGET_MIPS64) if (acc != 0) { tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); @@ -4398,7 +4445,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) } break; case OPC_MTHI: - case TX79_MMI_MTHI1: if (reg != 0) { #if defined(TARGET_MIPS64) if (acc != 0) { @@ -4413,7 +4459,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) } break; case OPC_MTLO: - case TX79_MMI_MTLO1: if (reg != 0) { #if defined(TARGET_MIPS64) if (acc != 0) { @@ -26500,11 +26545,11 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx) break; case TX79_MMI_MTLO1: case TX79_MMI_MTHI1: - gen_HILO(ctx, opc, 1, rs); + gen_HILO1_tx79(ctx, opc, rs); break; case TX79_MMI_MFLO1: case TX79_MMI_MFHI1: - gen_HILO(ctx, opc, 1, rd); + gen_HILO1_tx79(ctx, opc, rd); break; case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */