From patchwork Sun Apr 16 23:23:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 751197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w5ncR2cnSz9s75 for ; Mon, 17 Apr 2017 09:27:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="D5fKf/bS"; dkim-atps=neutral Received: from localhost ([::1]:33922 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cztZs-0005ns-RV for incoming@patchwork.ozlabs.org; Sun, 16 Apr 2017 19:27:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37954) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cztWj-0003mG-AY for qemu-devel@nongnu.org; Sun, 16 Apr 2017 19:24:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cztWf-0007wy-Cl for qemu-devel@nongnu.org; Sun, 16 Apr 2017 19:24:17 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:34951) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cztWf-0007wT-7B for qemu-devel@nongnu.org; Sun, 16 Apr 2017 19:24:13 -0400 Received: by mail-pf0-x243.google.com with SMTP id a188so22059686pfa.2 for ; Sun, 16 Apr 2017 16:24:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZkArrvFbJGfcjdT5msw5+fCYI6szHZMz+VsxFUstK60=; b=D5fKf/bSWQDkvi7EFEq9IujDBPPLVlkFo9a5iFrhQ4mNOrLGReYezRMJHDMJiV5bqN A3tunCCxAwf6LJuy6BisZ0yeFKoH+dtbh3V5aSVOfX9kU2kEs2XG7zbjlQv8VS4jpWrL DIVnQKDIOy6ozyIeg8iVWBB+pL/aoiXJLVgocmuijAlqAC2WtRkhCdXxIZ32uAbtxir+ 6ErruAK/EyeQuU2T2nZQ6DOpJSVLf0XNaodvJs9fy8QCQhfccoXTSnkEQQWrmHd08hSp vj5IUfXUDLA5dK/c85zKrXSnWQgjuKO36FK8HT5zBKUqVzrUQ/tGNEGo8y4Mwz7ixkoN 4XXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZkArrvFbJGfcjdT5msw5+fCYI6szHZMz+VsxFUstK60=; b=cakwHolqEEFKqBqtndjeOLK2iMEDv3Lj3vkhE5cvEyINug6GEjGuI+DND5Ug0B0gi4 G+p5CYioTG8jsLv3v1OOGW2NjeBQolAfcKDeJFZD9qegUh0juYkD/FtdiPGeBR1YLAU1 aNbwWcijHDjvnqHhPynatuyylp+e4V0bWQ/yZfYA4kEhGeJK0Qgva6IlmL7yMYw6YF/b mZyykUgo6SLiAMN+PNdszmE1J0in1IfIT9F/wxNGLhR7Khcp5cUcKDwP2VafxoC9HiLZ EKy9gFWpIy0FK+5FpzvAv4cnLwFkbWGoDYwBD4xJz4YbEpWVQM5JCZfLNs5IJ7JV1nrY I3Mw== X-Gm-Message-State: AN3rC/4jBC7fgGewwj+hXqUk/r8/1BBqmIntx72R7tqFri4n0kYGIlQQ TOtQxtqoNTbpyw== X-Received: by 10.98.68.133 with SMTP id m5mr9038950pfi.60.1492385052352; Sun, 16 Apr 2017 16:24:12 -0700 (PDT) Received: from localhost (z24.124-44-184.ppp.wakwak.ne.jp. [124.44.184.24]) by smtp.gmail.com with ESMTPSA id t2sm3864485pfl.34.2017.04.16.16.24.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 16 Apr 2017 16:24:11 -0700 (PDT) From: Stafford Horne To: qemu-devel@nongnu.org Date: Mon, 17 Apr 2017 08:23:52 +0900 Message-Id: X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 3/7] target/openrisc: add numcores and coreid support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , openrisc@lists.librecores.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These are used to identify the processor in SMP system. Their definition has been defined in verilog cores but it not yet part of the spec but it will be soon. The proposal for this is available: https://openrisc.io/proposals/core-identifier-and-number-of-cores Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/sys_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2eaff87..bd5051b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -227,6 +227,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, case TO_SPR(0, 64): /* ESR */ return env->esr; + case TO_SPR(0, 128): /* COREID */ + return 0; + + case TO_SPR(0, 129): /* NUMCORES */ + return 1; + case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb->dtlb[0][idx].mr;