diff mbox

[v3,2/8] i.MX: Standardize i.MX GPIO debug

Message ID f605b28ac0df20f1c87ab951b0a3f38417ac7007.1445637217.git.jcd@tribudubois.net
State New
Headers show

Commit Message

Jean-Christophe Dubois Oct. 24, 2015, 8:15 p.m. UTC
The goal is to have debug code always compiled during build.

We standardize all debug output on the following format:

[QOM_TYPE_NAME]reporting_function: debug message

We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
---

Changes since v1:
 * use HWADDR_PRIx for address formating
 * standardize qemu_log_mask on same model.
  
Changes since v2:
 * None

 hw/gpio/imx_gpio.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

Comments

Peter Crosthwaite Oct. 25, 2015, 1:45 a.m. UTC | #1
On Sat, Oct 24, 2015 at 1:15 PM, Jean-Christophe Dubois
<jcd@tribudubois.net> wrote:
> The goal is to have debug code always compiled during build.
>
> We standardize all debug output on the following format:
>
> [QOM_TYPE_NAME]reporting_function: debug message
>
> We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
> is following the same format as the above debug.
>

There are no IPRINTFs in the patch so drop this sentence.

Otherwise:

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>

> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
> ---
>
> Changes since v1:
>  * use HWADDR_PRIx for address formating
>  * standardize qemu_log_mask on same model.
>
> Changes since v2:
>  * None
>
>  hw/gpio/imx_gpio.c | 27 ++++++++++++++-------------
>  1 file changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
> index d56ffcd..3170585 100644
> --- a/hw/gpio/imx_gpio.c
> +++ b/hw/gpio/imx_gpio.c
> @@ -29,11 +29,12 @@ typedef enum IMXGPIOLevel {
>  } IMXGPIOLevel;
>
>  #define DPRINTF(fmt, args...) \
> -          do { \
> -              if (DEBUG_IMX_GPIO) { \
> -                  fprintf(stderr, "%s: " fmt , __func__, ##args); \
> -              } \
> -          } while (0)
> +    do { \
> +        if (DEBUG_IMX_GPIO) { \
> +            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
> +                                             __func__, ##args); \
> +        } \
> +    } while (0)
>
>  static const char *imx_gpio_reg_name(uint32_t reg)
>  {
> @@ -176,19 +177,19 @@ static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
>          if (s->has_edge_sel) {
>              reg_value = s->edge_sel;
>          } else {
> -            qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not "
> +            qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
>                            "present on this version of GPIO device\n",
>                            TYPE_IMX_GPIO, __func__);
>          }
>          break;
>
>      default:
> -        qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n",
> -                      TYPE_IMX_GPIO, __func__, (int)offset);
> +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
> +                      HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
>          break;
>      }
>
> -    DPRINTF("(%s) = 0x%"PRIx32"\n", imx_gpio_reg_name(offset), reg_value);
> +    DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
>
>      return reg_value;
>  }
> @@ -198,7 +199,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
>  {
>      IMXGPIOState *s = IMX_GPIO(opaque);
>
> -    DPRINTF("(%s, value = 0x%"PRIx32")\n", imx_gpio_reg_name(offset),
> +    DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
>              (uint32_t)value);
>
>      switch (offset) {
> @@ -238,15 +239,15 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
>              s->edge_sel = value;
>              imx_gpio_set_all_int_lines(s);
>          } else {
> -            qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not "
> +            qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
>                            "present on this version of GPIO device\n",
>                            TYPE_IMX_GPIO, __func__);
>          }
>          break;
>
>      default:
> -        qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n",
> -                      TYPE_IMX_GPIO, __func__, (int)offset);
> +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
> +                      HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
>          break;
>      }
>
> --
> 2.5.0
>
diff mbox

Patch

diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c
index d56ffcd..3170585 100644
--- a/hw/gpio/imx_gpio.c
+++ b/hw/gpio/imx_gpio.c
@@ -29,11 +29,12 @@  typedef enum IMXGPIOLevel {
 } IMXGPIOLevel;
 
 #define DPRINTF(fmt, args...) \
-          do { \
-              if (DEBUG_IMX_GPIO) { \
-                  fprintf(stderr, "%s: " fmt , __func__, ##args); \
-              } \
-          } while (0)
+    do { \
+        if (DEBUG_IMX_GPIO) { \
+            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
+                                             __func__, ##args); \
+        } \
+    } while (0)
 
 static const char *imx_gpio_reg_name(uint32_t reg)
 {
@@ -176,19 +177,19 @@  static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
         if (s->has_edge_sel) {
             reg_value = s->edge_sel;
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not "
+            qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
                           "present on this version of GPIO device\n",
                           TYPE_IMX_GPIO, __func__);
         }
         break;
 
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n",
-                      TYPE_IMX_GPIO, __func__, (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
         break;
     }
 
-    DPRINTF("(%s) = 0x%"PRIx32"\n", imx_gpio_reg_name(offset), reg_value);
+    DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
 
     return reg_value;
 }
@@ -198,7 +199,7 @@  static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
 {
     IMXGPIOState *s = IMX_GPIO(opaque);
 
-    DPRINTF("(%s, value = 0x%"PRIx32")\n", imx_gpio_reg_name(offset),
+    DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
             (uint32_t)value);
 
     switch (offset) {
@@ -238,15 +239,15 @@  static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
             s->edge_sel = value;
             imx_gpio_set_all_int_lines(s);
         } else {
-            qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not "
+            qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
                           "present on this version of GPIO device\n",
                           TYPE_IMX_GPIO, __func__);
         }
         break;
 
     default:
-        qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n",
-                      TYPE_IMX_GPIO, __func__, (int)offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
         break;
     }